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[209.132.180.131]) by mx.google.com with ESMTPS id w8si5535070igb.83.2015.09.10.02.03.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 10 Sep 2015 02:03:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-407028-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 68302 invoked by alias); 10 Sep 2015 09:03:09 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 68287 invoked by uid 89); 10 Sep 2015 09:03:08 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 10 Sep 2015 09:03:06 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-14-RyNF1FcdQx69-1X0--Yycg-1; Thu, 10 Sep 2015 10:03:01 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 10 Sep 2015 10:03:01 +0100 Message-ID: <55F14744.1070907@arm.com> Date: Thu, 10 Sep 2015 10:03:00 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM] PR 67439: Allow matching of *arm32_movhf when -mrestrict-it is on X-MC-Unique: RyNF1FcdQx69-1X0--Yycg-1 X-IsSubscribed: yes X-Original-Sender: kyrylo.tkachov@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::232 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi all, The ICE in this PR occurs when trying to compile code containing half-precision FP operations for Thumb2 with -mrestrict-it and an -mfpu that does not support fp16 (-mfpu=neon or lower). The problem is that we disable for -mrestrict-it the *arm32_movhf pattern that performs the move using only the general regs. Instead what we should do is allow the pattern to match but forbid its predication for -mrestrict-it by using the predicable_short_it attribute. This fixes the ICE. Bootstrap and test on arm is ok. This bug appears on the 5 and 4.9 branches as well. Ok for all active branches if testing there comes clean? Thanks, Kyrill 2015-09-10 Kyrylo Tkachov PR target/67439 * config/arm/arm.md (*arm32_movhf): Remove !arm_restrict_it from predicate. Set predicable_short_it attr to "no". 2015-09-10 Kyrylo Tkachov PR target/67439 * gcc.target/arm/pr67439_1.c: New test. commit b4888a0a5a9d2be30f99162a22ba2f22af46cbcd Author: Kyrylo Tkachov Date: Thu Sep 3 13:47:38 2015 +0100 [ARM] PR 67439: Allow matching of *arm32_movhf when -mrestrict-it is on diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 896deeb..fca9491 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6542,7 +6542,7 @@ (define_expand "movhf" (define_insn "*arm32_movhf" [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r") (match_operand:HF 1 "general_operand" " m,r,r,F"))] - "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) && !arm_restrict_it + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) && ( s_register_operand (operands[0], HFmode) || s_register_operand (operands[1], HFmode))" "* @@ -6580,7 +6580,8 @@ (define_insn "*arm32_movhf" [(set_attr "conds" "unconditional") (set_attr "type" "load1,store1,mov_reg,multiple") (set_attr "length" "4,4,4,8") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")] ) (define_expand "movsf" diff --git a/gcc/testsuite/gcc.target/arm/pr67439_1.c b/gcc/testsuite/gcc.target/arm/pr67439_1.c new file mode 100644 index 0000000..f7a6128 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr67439_1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O1 -mfp16-format=ieee -march=armv7-a -mfpu=neon -mthumb -mrestrict-it" } */ + +__fp16 h0 = -1.0; + +void +f (__fp16 *p) +{ + h0 = 1.0; +}