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[209.132.180.131]) by mx.google.com with ESMTPS id os5si30308586pac.92.2015.09.01.08.05.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Sep 2015 08:05:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-406445-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 128813 invoked by alias); 1 Sep 2015 15:04:48 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 128751 invoked by uid 89); 1 Sep 2015 15:04:48 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 01 Sep 2015 15:04:42 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-13-if_zSX5qTlG2gVvWPl2CRw-1; Tue, 01 Sep 2015 16:04:37 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 1 Sep 2015 16:04:37 +0100 Message-ID: <55E5BE85.2080200@arm.com> Date: Tue, 01 Sep 2015 16:04:37 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64][2/3] Implement negcc, notcc optabs X-MC-Unique: if_zSX5qTlG2gVvWPl2CRw-1 X-IsSubscribed: yes X-Original-Sender: kyrylo.tkachov@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::229 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi all, This second patch implements the new optabs for aarch64. The new expander is almost identical to the movcc expander except that operand 2 has a neg or a not before it to reflect the fact that it should be negated if the comparison in operand 1 holds. These patterns will eventually match to the CSNEG and CSINV instructions. The test included shows the kind of code that triggers this. We will now create a single immediate move followed by a CSNEG (or CSINV) rather than performing two immediate moves followed by a CSEL. Bootstrapped and tested on aarch64-none-linux-gnu. Ok for trunk if the midend changes in 1/3 are approved? Thanks, Kyrill 2015-09-01 Kyrylo Tkachov * config/aarch64/aarch64.md (cc): New define_expand. * config/aarch64/iterators.md (NEG_NOT): New code iterator. (neg_not_op): New code attribute. 2015-09-01 Kyrylo Tkachov * gcc.target/aarch64/cond_op_imm_1.c: New test. commit 771d788b184d466d1ea9fad87ab200601421f8c0 Author: Kyrylo Tkachov Date: Mon Jul 27 15:02:38 2015 +0100 [AArch64][2/3] Implement negcc, notcc optabs diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c3b985b..77bc7cd 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3038,6 +3038,24 @@ (define_expand "movcc" } ) +(define_expand "cc" + [(set (match_operand:GPI 0 "register_operand" "") + (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "") + (NEG_NOT:GPI (match_operand:GPI 2 "register_operand" "")) + (match_operand:GPI 3 "register_operand" "")))] + "" + { + rtx ccreg; + enum rtx_code code = GET_CODE (operands[1]); + + if (code == UNEQ || code == LTGT) + FAIL; + + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + } +) ;; CRC32 instructions. (define_insn "aarch64_" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index b8a45d1..64f5ade 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -668,6 +668,9 @@ (define_code_iterator LOGICAL [and ior xor]) ;; Code iterator for logical operations whose :nlogical works on SIMD registers. (define_code_iterator NLOGICAL [and ior]) +;; Code iterator for unary negate and bitwise complement. +(define_code_iterator NEG_NOT [neg not]) + ;; Code iterator for sign/zero extension (define_code_iterator ANY_EXTEND [sign_extend zero_extend]) @@ -797,6 +800,9 @@ (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") ;; Logical operator instruction mnemonics (define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) +;; Operation names for negate and bitwise complement. +(define_code_attr neg_not_op [(neg "neg") (not "not")]) + ;; Similar, but when not(op) (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) diff --git a/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c b/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c new file mode 100644 index 0000000..e93a693 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c @@ -0,0 +1,99 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ + +extern void abort (void); + +#define N 30 +#define M 25089992 + +int +foonegsi (int a) +{ + return a ? N : -N; +} + +/* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*" } } */ + + +int +fooinvsi (int a) +{ + return a ? N : ~N; +} + +/* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*" } } */ + + +long long +foonegdi (long long a) +{ + return a ? N : -N; +} + +long long +largefooneg (long long a) +{ + return a ? M : -M; +} + +/* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*" } } */ + +long long +fooinvdi (long long a) +{ + return a ? N : ~N; +} + +long long +largefooinv (long long a) +{ + return a ? M : ~M; +} + +/* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*" } } */ + + +int +main (void) +{ + if (foonegsi (1) != N) + abort (); + + if (foonegsi (0) != -N) + abort (); + + if (fooinvsi (1) != N) + abort (); + + if (fooinvsi (0) != ~N) + abort (); + + if (foonegdi (1) != N) + abort (); + + if (foonegdi (0) != -N) + abort (); + + if (fooinvdi (1) != N) + abort (); + + if (fooinvdi (0) != ~N) + abort (); + + if (largefooinv (0) != ~M) + abort (); + + if (largefooneg (0) != -M) + abort (); + + if (largefooinv (1) != M) + abort (); + + if (largefooneg (1) != M) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-not "csel\tx\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler-not "csel\tw\[0-9\]*.*" } } */