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[209.132.180.131]) by mx.google.com with ESMTPS id kh9si29002201pab.221.2015.09.01.03.08.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Sep 2015 03:08:33 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-406395-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 71906 invoked by alias); 1 Sep 2015 10:08:20 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 71373 invoked by uid 89); 1 Sep 2015 10:08:19 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 01 Sep 2015 10:08:18 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-10-4L3qiFtURj2Q__oTG5bDEQ-1; Tue, 01 Sep 2015 11:08:12 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 1 Sep 2015 11:08:10 +0100 Message-ID: <55E5790A.2090205@arm.com> Date: Tue, 01 Sep 2015 11:08:10 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , James Greenhalgh , Richard Earnshaw Subject: [PATCH][AArch64] Use preferred aliases for CSNEG, CSINC, CSINV X-MC-Unique: 4L3qiFtURj2Q__oTG5bDEQ-1 X-IsSubscribed: yes X-Original-Sender: kyrylo.tkachov@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22a as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi all, The ARMv8-A reference manual says: "CNEG , , is equivalent to CSNEG , , , invert() and is the preferred disassembly when Rn == Rm && cond != '111x'." That is, when the two input registers are the same we can use the shorter CNEG mnemonic with the inverse condition instead of the longer CSNEG instruction. Similarly for the CSINV and CSINC instructions, they have shorter CINV and CINC forms. This patch adjusts the output templates to emit the preferred shorter sequences when possible. The new mnemonics are just aliases, they map down to the same instruction in the end, so there are no performance or behaviour implications. But it does make the assembly a bit more readable IMO, since: "cneg w27, w9, le" can be simply read as "if the condition is less or equal negate w9" instead of the previous: "csneg w27, w9, w9, gt" where you have to remember which of the input registers is negated. Bootstrapped and tested on aarch64-linux-gnu. Ok for trunk? Thanks, Kyrill 2015-09-01 Kyrylo Tkachov * config/aarch64/aarch64.md (csinc3_insn): Use CINC mnemonic when possible. (*csinv3_insn): Use CINV mnemonic when possible. (csneg3_insn): USE CNEG mnemonic when possible. 2015-09-01 Kyrylo Tkachov * gcc.target/aarch64/abs_1.c: Update scan-assembler checks to allow cneg. * gcc.target/aarch64/cond_op_imm_1.c: Likewise. Likewise for cinv. * gcc.target/aarch64/mod_2.c: Likewise. commit 5f2598ffa7e0d7db92163cc5e8f4f26f7d2aff5a Author: Kyrylo Tkachov Date: Fri Aug 21 14:51:55 2015 +0100 [AArch64] Use preferred aliases for CSNEG, CSINC, CSINV diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 77bc7cd..2e4b26c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3090,7 +3090,12 @@ (define_insn "csinc3_insn" (const_int 1)) (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))] "" - "csinc\\t%0, %3, %2, %M1" + { + if (rtx_equal_p (operands[2], operands[3])) + return "cinc\\t%0, %2, %m1"; + else + return "csinc\\t%0, %3, %2, %M1"; + } [(set_attr "type" "csel")] ) @@ -3101,7 +3106,12 @@ (define_insn "*csinv3_insn" (not:GPI (match_operand:GPI 2 "register_operand" "r")) (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))] "" - "csinv\\t%0, %3, %2, %M1" + { + if (rtx_equal_p (operands[2], operands[3])) + return "cinv\\t%0, %2, %m1"; + else + return "csinv\\t%0, %3, %2, %M1"; + } [(set_attr "type" "csel")] ) @@ -3112,7 +3122,12 @@ (define_insn "csneg3_insn" (neg:GPI (match_operand:GPI 2 "register_operand" "r")) (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))] "" - "csneg\\t%0, %3, %2, %M1" + { + if (rtx_equal_p (operands[2], operands[3])) + return "cneg\\t%0, %2, %m1"; + else + return "csneg\\t%0, %3, %2, %M1"; + } [(set_attr "type" "csel")] ) diff --git a/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc/testsuite/gcc.target/aarch64/abs_1.c index 39364f4..84996a42 100644 --- a/gcc/testsuite/gcc.target/aarch64/abs_1.c +++ b/gcc/testsuite/gcc.target/aarch64/abs_1.c @@ -7,14 +7,14 @@ extern void abort (void); long long abs64 (long long a) { - /* { dg-final { scan-assembler "csneg\t" } } */ + /* { dg-final { scan-assembler "cs?neg\t" } } */ return llabs (a); } long long abs64_in_dreg (long long a) { - /* { dg-final { scan-assembler "csneg\t" } } */ + /* { dg-final { scan-assembler "cs?neg\t" } } */ register long long x asm ("d8") = a; register long long y asm ("d9"); asm volatile ("" : : "w" (x)); diff --git a/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c b/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c index e93a693..a5394cc 100644 --- a/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c +++ b/gcc/testsuite/gcc.target/aarch64/cond_op_imm_1.c @@ -12,7 +12,7 @@ foonegsi (int a) return a ? N : -N; } -/* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?neg\tw\[0-9\]*.*" } } */ int @@ -21,7 +21,7 @@ fooinvsi (int a) return a ? N : ~N; } -/* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?inv\tw\[0-9\]*.*" } } */ long long @@ -36,7 +36,7 @@ largefooneg (long long a) return a ? M : -M; } -/* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?neg\tx\[0-9\]*.*" } } */ long long fooinvdi (long long a) @@ -50,7 +50,7 @@ largefooinv (long long a) return a ? M : ~M; } -/* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*" } } */ +/* { dg-final { scan-assembler "cs?inv\tx\[0-9\]*.*" } } */ int diff --git a/gcc/testsuite/gcc.target/aarch64/mod_2.c b/gcc/testsuite/gcc.target/aarch64/mod_2.c index 2645c18..a49783d 100644 --- a/gcc/testsuite/gcc.target/aarch64/mod_2.c +++ b/gcc/testsuite/gcc.target/aarch64/mod_2.c @@ -3,5 +3,5 @@ #include "mod_2.x" -/* { dg-final { scan-assembler "csneg\t\[wx\]\[0-9\]*" } } */ +/* { dg-final { scan-assembler "cs?neg\t\[wx\]\[0-9\]*" } } */ /* { dg-final { scan-assembler-times "and\t\[wx\]\[0-9\]*" 1 } } */