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[70.162.241.179]) by mx.google.com with ESMTPSA id u8sm30685576pdj.46.2015.06.25.10.08.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jun 2015 10:08:11 -0700 (PDT) Message-ID: <558C3576.3070108@linaro.org> Date: Thu, 25 Jun 2015 10:08:06 -0700 From: Michael Collison User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [ARM] Optimize compare against smin/umin X-Original-Sender: michael.collison@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::230 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 This patch is designed to optimize constructs such as: #define min(x, y) ((x) <= (y)) ? (x) : (y) unsignedint foo (unsignedint i, unsignedint x ,unsignedint y) { return i < (min (x, y)); } int bar (int i,int x,int y) { return i < (min (x, y)); } Patch was tested on arm-linux-gnueabi, arm-linux-gnueabihf, armeb-linux-gnueabihf. Okay for trunk? 2015-06-24 Michael Collison * gcc/config/arm/arm.md (*arm_smin_cmp): New pattern. (*arm_umin_cmp): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 1ac8af0..994c95f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3455,6 +3455,28 @@ (set_attr "type" "multiple,multiple")] ) +;; t = (s/u)min (x, y) +;; cc = cmp (t, z) +;; is the same as +;; cmp x, z +;; cmpge(u) y, z + +(define_insn_and_split "*arm_smin_cmp" + [(set (reg:CC CC_REGNUM) + (compare:CC + (smin:SI (match_operand:SI 0 "s_register_operand" "r") + (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_32BIT" + "#" + "" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 0) (match_dup 2))) + (cond_exec (ge:CC (reg:CC CC_REGNUM) (const_int 0)) + (set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))))] +) + (define_expand "umaxsi3" [(parallel [ (set (match_operand:SI 0 "s_register_operand" "") @@ -3521,6 +3543,22 @@ (set_attr "type" "store1")] ) +(define_insn_and_split "*arm_umin_cmp" + [(set (reg:CC CC_REGNUM) + (compare:CC + (umin:SI (match_operand:SI 0 "s_register_operand" "r") + (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_32BIT" + "#" + "" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 0) (match_dup 2))) + (cond_exec (geu:CC (reg:CC CC_REGNUM) (const_int 0)) + (set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))))] +) + (define_insn "*store_minmaxsi" [(set (match_operand:SI 0 "memory_operand" "=m") (match_operator:SI 3 "minmax_operator"