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[209.132.180.131]) by mx.google.com with ESMTPS id n1si12621328pdj.42.2014.08.12.07.37.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Aug 2014 07:37:47 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-374918-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 26785 invoked by alias); 12 Aug 2014 14:37:35 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 26743 invoked by uid 89); 12 Aug 2014 14:37:31 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: collaborate-mta1.arm.com Received: from fw-tnat.austin.arm.com (HELO collaborate-mta1.arm.com) (217.140.110.23) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Aug 2014 14:37:29 +0000 Received: from [10.1.209.140] (e105545-lin.cambridge.arm.com [10.1.209.140]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 46D8E13F91D for ; Tue, 12 Aug 2014 09:37:27 -0500 (CDT) Message-ID: <53EA26A7.2020606@arm.com> Date: Tue, 12 Aug 2014 15:37:27 +0100 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.0 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [Patch ARM] Fix PR target/62098 - vcvt generation. X-IsSubscribed: yes X-Original-Sender: ramana.radhakrishnan@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c03::22d as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, This fixes the issue in PR target/62098 where the pattern is clearly bogus and it's not clear what I was thinking when I ok'd it. The vcvt instruction in this form writes to it's source register and this should have been modelled correctly in the backend in this form rather than the bogus pattern that we managed to generate. Tested cross on arm-none-linux-gnueabihf with no regressions, verified that the testcase from the bug report clearly DTRT. I haven't yet dealt with a testcase but that will follow suit. Applied so far on trunk after cross-testing on armv7-a, neon, float-abi=hard, arm state and will backport to 4.9 after suitable testing there along with the afore mentioned testcase. regards Ramana 2014-08-12 Ramana Radhakrishnan PR target/62098 * config/arm/vfp.md (*combine_vcvtf2i): Fix constraint. Remove unnecessary attributes. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index ab502ad..0059689 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1264,17 +1264,15 @@ ) (define_insn "*combine_vcvtf2i" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t") + [(set (match_operand:SI 0 "s_register_operand" "=t") + (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0") (match_operand 2 "const_double_vcvt_power_of_two" "Dp")))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" - "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1" + "vcvt%?.s32.f32\\t%0, %1, %v2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "ce_count" "2") - (set_attr "type" "f_cvtf2i") - (set_attr "length" "8")] + (set_attr "type" "f_cvtf2i")] ) ;; Store multiple insn used in function prologue.