From patchwork Wed Nov 30 10:20:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 84996 Delivered-To: patch@linaro.org Received: by 10.182.112.6 with SMTP id im6csp208105obb; Wed, 30 Nov 2016 02:20:58 -0800 (PST) X-Received: by 10.98.223.25 with SMTP id u25mr32163895pfg.96.1480501258847; Wed, 30 Nov 2016 02:20:58 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 123si63623872pgh.10.2016.11.30.02.20.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Nov 2016 02:20:58 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-443016-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-443016-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-443016-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=OO49J+uMpx0enVekz /74JpT60mMQFU9YqAH6q52vv4ffWo6ZZ0E6P1k78+i+SoSzFLS+TMKgRygrFRqxO ygnskYGcblAFpzRwKzyZuX61gmsNdaKkzhJCIWzeeERhpwQrm/mtFntfefHHuy2X /5oAr9IhLBCgBrVLgguMjXNhY4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=2CJ/xIILAic9DxzUzWrTifR UVVE=; b=ASVDz6r+TEscHctsd5Zq8CdM98Mn/GygWn2bucwG3BEBfBg6eq1GUVB CTeEAmWHT44djzsmG3ug3TZeAKPR6zmfjxHGVNse+gZcoNI1gunXLfBudErNGa2G SQxaB7B+M1x3BHeqTCuPjHrVUuTjup398bcGJnPbzwVZ93rphA48= Received: (qmail 45215 invoked by alias); 30 Nov 2016 10:20:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 45194 invoked by uid 89); 30 Nov 2016 10:20:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.5 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=rk, rr, sk:empty_f, UD:empty_fiq_handler.c X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 30 Nov 2016 10:20:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E541FAD7; Wed, 30 Nov 2016 02:20:31 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 303CE3F24D; Wed, 30 Nov 2016 02:20:31 -0800 (PST) Subject: Re: [PATCH, GCC/ARM] Fix ICE when compiling empty FIQ interrupt handler in ARM mode To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <0ce9ef69-cf59-075e-d392-f5bed829c4d8@foss.arm.com> <582C2946.6030900@foss.arm.com> From: Thomas Preudhomme Message-ID: <5326d119-ded9-4cb1-c13b-61f7a0c85f2e@foss.arm.com> Date: Wed, 30 Nov 2016 10:20:29 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <582C2946.6030900@foss.arm.com> X-IsSubscribed: yes Hi, Is this ok to backport this fix together with its follow-up testcase fix to gcc-5-branch and gcc-6-branch? Both patches apply cleanly (patches attached for reference). 2016-11-30 Thomas Preud'homme Backport from mainline 2016-11-16 Thomas Preud'homme gcc/ * config/arm/arm.md (arm_addsi3): Add alternative for addition of general register with general register or ARM constant into SP register. gcc/testsuite/ * gcc.target/arm/empty_fiq_handler.c: New test. Backport from mainline 2016-11-21 Thomas Preud'homme gcc/testsuite/ * gcc.target/arm/empty_fiq_handler.c: Skip if -mthumb is passed in and target is Thumb-only. Best regards, Thomas On 16/11/16 09:39, Kyrill Tkachov wrote: > > On 09/11/16 16:19, Thomas Preudhomme wrote: >> Hi, >> >> This patch fixes the following ICE when building when compiling an empty FIQ >> interrupt handler in ARM mode: >> >> empty_fiq_handler.c:5:1: error: insn does not satisfy its constraints: >> } >> ^ >> >> (insn/f 13 12 14 (set (reg/f:SI 13 sp) >> (plus:SI (reg/f:SI 11 fp) >> (const_int 4 [0x4]))) irq.c:5 4 {*arm_addsi3} >> (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:SI 13 sp) >> (plus:SI (reg/f:SI 11 fp) >> (const_int 4 [0x4]))) >> (nil))) >> >> The ICE was provoked by missing an alternative to reflect that ARM mode can do >> an add of general register into sp which is unpredictable in Thumb mode add >> immediate. >> >> ChangeLog entries are as follow: >> >> *** gcc/ChangeLog *** >> >> 2016-11-04 Thomas Preud'homme >> >> * config/arm/arm.md (arm_addsi3): Add alternative for addition of >> general register with general register or ARM constant into SP >> register. >> >> >> *** gcc/testsuite/ChangeLog *** >> >> 2016-11-04 Thomas Preud'homme >> >> * gcc.target/arm/empty_fiq_handler.c: New test. >> >> >> Testing: bootstrapped on ARMv7-A ARM mode & testsuite shows no regression. >> >> Is this ok for trunk? >> > > I see that "r" does not include the stack pointer (STACK_REG is separate from > GENERAL_REGs) so we are indeed missing > that constraint. > > Ok for trunk. > Thanks, > Kyrill > >> Best regards, >> >> Thomas > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 47171b99682207226aa4f9a76d4dfb54d6c2814b..86df1c0366be6c4b9b4ebf76821a8100c4e9fc16 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -575,9 +575,9 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") - (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk") + (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %0, %2 @@ -587,6 +587,7 @@ add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 + add%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 @@ -606,10 +607,10 @@ operands[1], 0); DONE; " - [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (const_string "alu_imm") (const_string "alu_sreg"))) diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c new file mode 100644 index 0000000000000000000000000000000000000000..8313f2199122be153a737946e817a5e3bee60372 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */ + +/* Below code used to trigger an ICE due to missing constraints for + sp = fp + cst pattern. */ + +void fiq_handler (void) __attribute__((interrupt ("FIQ"))); + +void +fiq_handler (void) +{ +}