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[209.132.180.131]) by mx.google.com with ESMTPS id w197si4567794ywd.487.2016.11.21.03.03.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Nov 2016 03:03:31 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-442114-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-442114-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-442114-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=gIHZKq+a76ock2tkB Dgl+Bi/MqWvkDUOYZhn7iXgDdJ/GaT7q9W2LHUbNnl79/R4XEW/E5gHavHq1GeBX GFLUaD7Se4yxp5K/18BO/QE+/nz+rJA5SZg8EmCklnpAveLy7fhUDETjPVaKIKdQ 4UiDd+K7zBTOAv23QspHxGZuDA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=jiUow2NxmAiyNFUlDKcoKgZ yhtc=; b=GYD4tLWQL31nfGgqp6WGile28MvGGv5c5EfwUPW+jnrxtKaegYEPwgI 6BpiIlAKl9qY2oG8Uqm+/wgb5L9zDwTgURcOtw6m3dpTUwx5pgIcEztmCk0V7ci1 aX3TAdT6xasuYw+M/uh2vE3OEknbQjF5qwc3URTQtqRHvfvA58MA= Received: (qmail 12256 invoked by alias); 21 Nov 2016 11:03:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 12246 invoked by uid 89); 21 Nov 2016 11:03:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=sk:kyrylo, kyrylo.tkachov@foss.arm.com, U*kyrylo.tkachov, sk:kyrylo. X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 Nov 2016 11:03:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89A7428; Mon, 21 Nov 2016 03:03:03 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A84713F220; Mon, 21 Nov 2016 03:03:02 -0800 (PST) Subject: Re: [PATCH, GCC/ARM] Fix ICE when compiling empty FIQ interrupt handler in ARM mode To: Christophe Lyon , Kyrill Tkachov References: <0ce9ef69-cf59-075e-d392-f5bed829c4d8@foss.arm.com> <582C2946.6030900@foss.arm.com> Cc: Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme Message-ID: <50564bc7-7f41-f41e-b50f-9fb9589cdca7@foss.arm.com> Date: Mon, 21 Nov 2016 11:03:01 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes On 17/11/16 20:04, Thomas Preudhomme wrote: > Hi Christophe, > > On 17/11/16 13:36, Christophe Lyon wrote: >> On 16 November 2016 at 10:39, Kyrill Tkachov >> wrote: >>> >>> On 09/11/16 16:19, Thomas Preudhomme wrote: >>>> >>>> Hi, >>>> >>>> This patch fixes the following ICE when building when compiling an empty >>>> FIQ interrupt handler in ARM mode: >>>> >>>> empty_fiq_handler.c:5:1: error: insn does not satisfy its constraints: >>>> } >>>> ^ >>>> >>>> (insn/f 13 12 14 (set (reg/f:SI 13 sp) >>>> (plus:SI (reg/f:SI 11 fp) >>>> (const_int 4 [0x4]))) irq.c:5 4 {*arm_addsi3} >>>> (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:SI 13 sp) >>>> (plus:SI (reg/f:SI 11 fp) >>>> (const_int 4 [0x4]))) >>>> (nil))) >>>> >>>> The ICE was provoked by missing an alternative to reflect that ARM mode >>>> can do an add of general register into sp which is unpredictable in Thumb >>>> mode add immediate. >>>> >>>> ChangeLog entries are as follow: >>>> >>>> *** gcc/ChangeLog *** >>>> >>>> 2016-11-04 Thomas Preud'homme >>>> >>>> * config/arm/arm.md (arm_addsi3): Add alternative for addition of >>>> general register with general register or ARM constant into SP >>>> register. >>>> >>>> >>>> *** gcc/testsuite/ChangeLog *** >>>> >>>> 2016-11-04 Thomas Preud'homme >>>> >>>> * gcc.target/arm/empty_fiq_handler.c: New test. >>>> >>>> >>>> Testing: bootstrapped on ARMv7-A ARM mode & testsuite shows no regression. >>>> >>>> Is this ok for trunk? >>>> >>> >>> I see that "r" does not include the stack pointer (STACK_REG is separate >>> from GENERAL_REGs) so we are indeed missing >>> that constraint. >>> >>> Ok for trunk. >>> Thanks, >>> Kyrill >>> >>>> Best regards, >>>> >>>> Thomas >>> >>> >> >> Hi Thomas, >> >> The new test fails when compiled with -mthumb -march=armv5t: >> gcc.target/arm/empty_fiq_handler.c: In function 'fiq_handler': >> gcc.target/arm/empty_fiq_handler.c:11:1: error: interrupt Service >> Routines cannot be coded in Thumb mode > > Right, interrupt handler can only be compiled in the mode where the CPU boots. > So for non Thumb-only targets it should be compiled with -marm. I'll push a > patch tomorrow. I've committed the following patch as obvious: Interrupt handlers on ARM can only be compiled in the execution mode where the processor boot. That is -mthumb for Thumb-only devices, -marm otherwise. This changes the empty_fiq_handler to skip the test when -mthumb is passed but the processor boot in ARM mode. ChangeLog entry is as follows: *** gcc/testsuite/ChangeLog *** 2016-11-17 Thomas Preud'homme * gcc.target/arm/empty_fiq_handler.c: Skip if -mthumb is passed in and target is Thumb-only. Best regards, Thomas diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c index bbcfd0e32f9d0cc60c8a013fd1bb584b21aaad16..8313f2199122be153a737946e817a5e3bee60372 100644 --- a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */ /* Below code used to trigger an ICE due to missing constraints for sp = fp + cst pattern. */