From patchwork Thu Dec 15 16:07:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 88187 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp881768qgi; Thu, 15 Dec 2016 08:09:43 -0800 (PST) X-Received: by 10.84.138.165 with SMTP id 34mr4053620plp.20.1481818183560; Thu, 15 Dec 2016 08:09:43 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id n21si3108634pgj.254.2016.12.15.08.09.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Dec 2016 08:09:43 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444529-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444529-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444529-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=Fl8VmnCxRW6gZUjZHArPwZJSKfoSR f7h15RRjEbnBeky2+itGBBqbZ8Z/XisdtqTAmKWtio0wZknoTJB9gzhLUficyXRE EhWVcMFiJg8ASXlkHp8dZvWDuMLZrtTN8lNEyw0dbpHEv1OxdR3ldZUaoIc0W0JF nBlL1G05eg6mfQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=0GBH2X5SCRwSgZNEKK9FPVdmnX0=; b=sgC mVuu8jPpmzaYwt7rc1YJLdpqccysh86BhmCPVb4rF4VhnlhsSjcVFrhVhsLpAVLK pDiD/8OJHO7pT40ZKa29ohZrFaBFDma7V67WkM/mikzjo2jiM5nxD2KNrpywq5Oh WckzW5Wv+BVCVCevBGXbT41rarDuZcVzyTY4mTBM= Received: (qmail 40471 invoked by alias); 15 Dec 2016 16:07:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 40291 invoked by uid 89); 15 Dec 2016 16:07:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:07:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB18F1516; Thu, 15 Dec 2016 08:07:22 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4C1E33F445 for ; Thu, 15 Dec 2016 08:07:22 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 13/21] [arm] Remove FPU rev field To: gcc-patches@gcc.gnu.org References: Message-ID: <4d2775ef-0e3a-5e67-04ff-d4b862c24a74@arm.com> Date: Thu, 15 Dec 2016 16:07:20 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: Similar to the main ISA, we convert the FPU revision into a set of feature bits. This permits a more complex set of capability relationships to be expressed more easily. For now we continue to use the traditional bitmasks. * arm.h (FPU_FL_VFPv2) New feature bit. (FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise. (FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper macros. (FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise. (TARGET_FPU_REV): Delete. (TARGET_VFP3): Use feature bits. (TARGET_VFP5): Likewise. (TARGET_FMA): Likewise. (TARGET_FPU_ARMV8): Likewise. (struct arm_fpu_desc): Delete rev field. * arm-fpus.def: Delete REV entry, use new feature bits and macros. * arm.c (all_fpus): Delete rev field. --- gcc/config/arm/arm-fpus.def | 44 ++++++++++++++++++++++---------------------- gcc/config/arm/arm.c | 4 ++-- gcc/config/arm/arm.h | 28 ++++++++++++++++++++++------ 3 files changed, 46 insertions(+), 30 deletions(-) diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index eca03bb..25e2ebd 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -19,31 +19,31 @@ /* Before using #include to read this file, define a macro: - ARM_FPU(NAME, REV, FEATURES) + ARM_FPU(NAME, FEATURES) The arguments are the fields of struct arm_fpu_desc. genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_FPU("vfp", 2, FPU_FL_DBL) -ARM_FPU("vfpv2", 2, FPU_FL_DBL) -ARM_FPU("vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL) -ARM_FPU("vfpv3-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16) -ARM_FPU("vfpv3-d16", 3, FPU_FL_DBL) -ARM_FPU("vfpv3-d16-fp16", 3, FPU_FL_DBL | FPU_FL_FP16) -ARM_FPU("vfpv3xd", 3, FPU_FL_NONE) -ARM_FPU("vfpv3xd-fp16", 3, FPU_FL_FP16) -ARM_FPU("neon", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON) -ARM_FPU("neon-vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON) -ARM_FPU("neon-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16) -ARM_FPU("vfpv4-d16", 4, FPU_FL_DBL | FPU_FL_FP16) -ARM_FPU("fpv4-sp-d16", 4, FPU_FL_FP16) -ARM_FPU("fpv5-sp-d16", 5, FPU_FL_FP16) -ARM_FPU("fpv5-d16", 5, FPU_FL_DBL | FPU_FL_FP16) -ARM_FPU("neon-vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16) -ARM_FPU("neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("crypto-neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO) +ARM_FPU("vfp", FPU_VFPv2 | FPU_DBL) +ARM_FPU("vfpv2", FPU_VFPv2 | FPU_DBL) +ARM_FPU("vfpv3", FPU_VFPv3 | FPU_D32) +ARM_FPU("vfpv3-fp16", FPU_VFPv3 | FPU_D32 | FPU_FP16) +ARM_FPU("vfpv3-d16", FPU_VFPv3 | FPU_DBL) +ARM_FPU("vfpv3-d16-fp16", FPU_VFPv3 | FPU_DBL | FPU_FP16) +ARM_FPU("vfpv3xd", FPU_VFPv3) +ARM_FPU("vfpv3xd-fp16", FPU_VFPv3 | FPU_FP16) +ARM_FPU("neon", FPU_VFPv3 | FPU_NEON) +ARM_FPU("neon-vfpv3", FPU_VFPv3 | FPU_NEON) +ARM_FPU("neon-fp16", FPU_VFPv3 | FPU_NEON | FPU_FP16) +ARM_FPU("vfpv4", FPU_VFPv4 | FPU_D32 | FPU_FP16) +ARM_FPU("vfpv4-d16", FPU_VFPv4 | FPU_DBL | FPU_FP16) +ARM_FPU("fpv4-sp-d16", FPU_VFPv4 | FPU_FP16) +ARM_FPU("fpv5-sp-d16", FPU_VFPv5 | FPU_FP16) +ARM_FPU("fpv5-d16", FPU_VFPv5 | FPU_DBL | FPU_FP16) +ARM_FPU("neon-vfpv4", FPU_VFPv4 | FPU_NEON | FPU_FP16) +ARM_FPU("fp-armv8", FPU_ARMv8 | FPU_D32 | FPU_FP16) +ARM_FPU("neon-fp-armv8", FPU_ARMv8 | FPU_NEON | FPU_FP16) +ARM_FPU("crypto-neon-fp-armv8", FPU_ARMv8 | FPU_CRYPTO | FPU_FP16) /* Compatibility aliases. */ -ARM_FPU("vfp3", 3, FPU_FL_D32 | FPU_FL_DBL) +ARM_FPU("vfp3", FPU_VFPv3 | FPU_D32) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 820a6ab..e555cf6 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2323,8 +2323,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__"; const struct arm_fpu_desc all_fpus[] = { -#define ARM_FPU(NAME, REV, FEATURES) \ - { NAME, REV, FEATURES }, +#define ARM_FPU(NAME, FEATURES) \ + { NAME, FEATURES }, #include "arm-fpus.def" #undef ARM_FPU }; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index a412fb1..332f0fa 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -164,10 +164,10 @@ extern tree arm_fp16_type_node; #define TARGET_VFPD32 (TARGET_FPU_FEATURES & FPU_FL_D32) /* FPU supports VFPv3 instructions. */ -#define TARGET_VFP3 (TARGET_FPU_REV >= 3) +#define TARGET_VFP3 (TARGET_FPU_FEATURES & FPU_FL_VFPv3) /* FPU supports FPv5 instructions. */ -#define TARGET_VFP5 (TARGET_FPU_REV >= 5) +#define TARGET_VFP5 (TARGET_FPU_FEATURES & FPU_FL_VFPv5) /* FPU only supports VFP single-precision instructions. */ #define TARGET_VFP_SINGLE ((TARGET_FPU_FEATURES & FPU_FL_DBL) == 0) @@ -190,10 +190,10 @@ extern tree arm_fp16_type_node; (TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5)) /* FPU supports fused-multiply-add operations. */ -#define TARGET_FMA (TARGET_FPU_REV >= 4) +#define TARGET_FMA (TARGET_FPU_FEATURES & FPU_FL_VFPv4) /* FPU is ARMv8 compatible. */ -#define TARGET_FPU_ARMV8 (TARGET_FPU_REV >= 8) +#define TARGET_FPU_ARMV8 (TARGET_FPU_FEATURES & FPU_FL_ARMv8) /* FPU supports Crypto extensions. */ #define TARGET_CRYPTO \ @@ -341,18 +341,34 @@ typedef unsigned long arm_fpu_feature_set; #define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */ #define FPU_FL_DBL (1u << 3) /* Has double precision. */ #define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */ +#define FPU_FL_VFPv2 (1u << 5) /* Has VFPv2 features. */ +#define FPU_FL_VFPv3 (1u << 6) /* Has VFPv3 extensions. */ +#define FPU_FL_VFPv4 (1u << 7) /* Has VFPv4 extensions. */ +#define FPU_FL_VFPv5 (1u << 8) /* Has VFPv5 extensions. */ +#define FPU_FL_ARMv8 (1u << 9) /* Has ARMv8 extensions to VFP. */ + +/* Some useful combinations. */ +#define FPU_VFPv2 (FPU_FL_VFPv2) +#define FPU_VFPv3 (FPU_VFPv2 | FPU_FL_VFPv3) +#define FPU_VFPv4 (FPU_VFPv3 | FPU_FL_VFPv4) +#define FPU_VFPv5 (FPU_VFPv4 | FPU_FL_VFPv5) +#define FPU_ARMv8 (FPU_VFPv5 | FPU_FL_ARMv8) + +#define FPU_DBL (FPU_FL_DBL) +#define FPU_D32 (FPU_DBL | FPU_FL_D32) +#define FPU_NEON (FPU_D32 | FPU_FL_NEON) +#define FPU_CRYPTO (FPU_NEON | FPU_FL_CRYPTO) +#define FPU_FP16 (FPU_FL_FP16) extern const struct arm_fpu_desc { const char *name; - int rev; arm_fpu_feature_set features; } all_fpus[]; /* Accessors. */ #define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name) -#define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev) #define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features) /* Which floating point hardware to schedule for. */