From patchwork Tue Feb 28 16:20:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 6974 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id AA0F723EA9 for ; Tue, 28 Feb 2012 16:20:58 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 58C43A1886C for ; Tue, 28 Feb 2012 16:20:58 +0000 (UTC) Received: by yhpp61 with SMTP id p61so1761428yhp.11 for ; Tue, 28 Feb 2012 08:20:57 -0800 (PST) Received: from mr.google.com ([10.50.95.230]) by 10.50.95.230 with SMTP id dn6mr2839662igb.0.1330446057834 (num_hops = 1); Tue, 28 Feb 2012 08:20:57 -0800 (PST) Received: by 10.50.95.230 with SMTP id dn6mr2308938igb.0.1330446057793; Tue, 28 Feb 2012 08:20:57 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.11.10 with SMTP id r10csp12049ibr; Tue, 28 Feb 2012 08:20:56 -0800 (PST) Received: by 10.14.183.130 with SMTP id q2mr8716824eem.101.1330446055825; Tue, 28 Feb 2012 08:20:55 -0800 (PST) Received: from relay1.mentorg.com (relay1.mentorg.com. [192.94.38.131]) by mx.google.com with ESMTPS id o15si10436195eea.20.2012.02.28.08.20.55 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 28 Feb 2012 08:20:55 -0800 (PST) Received-SPF: neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) client-ip=192.94.38.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) smtp.mail=Andrew_Stubbs@mentor.com Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1S2Pn0-0001qb-WC from Andrew_Stubbs@mentor.com ; Tue, 28 Feb 2012 08:20:35 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 28 Feb 2012 08:20:28 -0800 Received: from [172.30.11.195] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Tue, 28 Feb 2012 16:20:25 +0000 Message-ID: <4F4CFEC6.2090705@codesourcery.com> Date: Tue, 28 Feb 2012 16:20:22 +0000 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" , "patches@linaro.org" Subject: [PATCH][ARM] NEON DImode immediate constants X-OriginalArrivalTime: 28 Feb 2012 16:20:28.0348 (UTC) FILETIME=[E25E87C0:01CCF634] X-Gm-Message-State: ALoCoQkNcE9+6iPU7rWZmziABi82dmFMz3P8tWj/ZAffR8XDYLZ9EVkyzqWyvZSweQGouH/kTr56 Hi all, This patch implements 64-bit immediate constant loads in NEON. The current state is that you can load const_vector, but not const_int. This is clearly not ideal. The result is a constant pool entry when it's not necessary. The patch disables the movdi_vfp patterns for loading DImode values, if the operand is const_int and NEON is enabled, and extends the neon_mov pattern to include DImode const_int, as well as the const_vector operands. I've modified neon_valid_immediate only enough to accept const_int input - the logic remains untouched. OK for 4.8? Andrew 2012-02-28 Andrew Stubbs gcc/ * config/arm/arm.c (neon_valid_immediate): Allow const_int. * config/arm/constraints.md (Dn): Allow const_int. * config/arm/neon.md (neon_mov): Use VDX to allow DImode. * config/arm/predicates.md (imm_for_neon_mov_operand): Allow const_int. * config/arm/vfp.md (movdi_vfp): Disable for const_int when neon is enabled. (movdi_vfp_cortexa8): Likewise. --- gcc/config/arm/arm.c | 20 +++++++++++++++++--- gcc/config/arm/constraints.md | 6 +++--- gcc/config/arm/neon.md | 4 ++-- gcc/config/arm/predicates.md | 2 +- gcc/config/arm/vfp.md | 6 ++++-- 5 files changed, 27 insertions(+), 11 deletions(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 0bded8d..ea2a256 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8873,11 +8873,25 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, break; \ } - unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); - unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); + unsigned int i, elsize = 0, idx = 0, n_elts; + unsigned int innersize; unsigned char bytes[16]; int immtype = -1, matches; unsigned int invmask = inverse ? 0xff : 0; + bool vector = GET_CODE (op) == CONST_VECTOR; + + if (vector) + { + n_elts = CONST_VECTOR_NUNITS (op); + innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); + } + else + { + n_elts = 1; + if (mode == VOIDmode) + mode = DImode; + innersize = GET_MODE_SIZE (mode); + } /* Vectors of float constants. */ if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) @@ -8913,7 +8927,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, /* Splat vector constant out into a byte vector. */ for (i = 0; i < n_elts; i++) { - rtx el = CONST_VECTOR_ELT (op, i); + rtx el = vector ? CONST_VECTOR_ELT (op, i) : op; unsigned HOST_WIDE_INT elpart; unsigned int part, parts; diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 7d0269a..68979c1 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -255,9 +255,9 @@ (define_constraint "Dn" "@internal - In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov - immediate instruction." - (and (match_code "const_vector") + In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a + Neon vmov immediate instruction." + (and (match_code "const_vector,const_int") (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, GET_MODE (op))"))) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index d7caa37..757be01 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -152,9 +152,9 @@ (define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd")) (define_insn "*neon_mov" - [(set (match_operand:VD 0 "nonimmediate_operand" + [(set (match_operand:VDX 0 "nonimmediate_operand" "=w,Uv,w, w, ?r,?w,?r,?r, ?Us") - (match_operand:VD 1 "general_operand" + (match_operand:VDX 1 "general_operand" " w,w, Dn,Uvi, w, r, r, Usi,r"))] "TARGET_NEON && (register_operand (operands[0], mode) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index b535335..8a8a1f1 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -630,7 +630,7 @@ }) (define_predicate "imm_for_neon_mov_operand" - (match_code "const_vector") + (match_code "const_vector,const_int") { return neon_immediate_valid_for_move (op, mode, NULL, NULL); }) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 6530570..2cc4104 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -138,7 +138,8 @@ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" + || register_operand (operands[1], DImode)) + && (!TARGET_NEON || !CONST_INT_P (operands[1]))" "* switch (which_alternative) { @@ -187,7 +188,8 @@ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" + || register_operand (operands[1], DImode)) + && (!TARGET_NEON || !CONST_INT_P (operands[1]))" "* switch (which_alternative) {