From patchwork Tue Dec 6 17:59:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 5520 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B651023E11 for ; Tue, 6 Dec 2011 17:59:57 +0000 (UTC) Received: from mail-ee0-f52.google.com (mail-ee0-f52.google.com [74.125.83.52]) by fiordland.canonical.com (Postfix) with ESMTP id 9C644A1864C for ; Tue, 6 Dec 2011 17:59:57 +0000 (UTC) Received: by eekc14 with SMTP id c14so1189338eek.11 for ; Tue, 06 Dec 2011 09:59:57 -0800 (PST) Received: by 10.14.9.163 with SMTP id 35mr2932197eet.234.1323194397418; Tue, 06 Dec 2011 09:59:57 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs48844bkc; Tue, 6 Dec 2011 09:59:57 -0800 (PST) Received: by 10.180.98.70 with SMTP id eg6mr18896707wib.46.1323194395581; Tue, 06 Dec 2011 09:59:55 -0800 (PST) Received: from relay1.mentorg.com (relay1.mentorg.com. [192.94.38.131]) by mx.google.com with ESMTPS id cf10si11717388wib.83.2011.12.06.09.59.55 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 06 Dec 2011 09:59:55 -0800 (PST) Received-SPF: neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) client-ip=192.94.38.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) smtp.mail=Andrew_Stubbs@mentor.com Received: from nat-ies.mentorg.com ([192.94.31.2] helo=EU1-MAIL.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1RXzJ2-0000eu-TQ from Andrew_Stubbs@mentor.com ; Tue, 06 Dec 2011 09:59:53 -0800 Received: from [172.30.64.180] ([172.30.64.180]) by EU1-MAIL.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 6 Dec 2011 17:59:51 +0000 Message-ID: <4EDE5810.1070204@codesourcery.com> Date: Tue, 06 Dec 2011 17:59:44 +0000 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: "patches@linaro.org" Subject: [PATCH][ARM] one_cmpldi2 in NEON X-OriginalArrivalTime: 06 Dec 2011 17:59:51.0334 (UTC) FILETIME=[D9E2FC60:01CCB440] This patch adds a one's complement pattern for doing DImode 'not' in NEON registers. There are already patterns for doing one's complement of vectors, and even though it boils down to the same instruction, the DImode case was missing. The patch needs to be a little more complicated than using a mode iterator that includes DI because it needs to coexist with the non-neon one_cmpldi2 (renamed by this patch to "one_cmpldi2_core"). OK for when stage 1 opens again? Andrew 2011-12-06 Andrew Stubbs gcc/ * config/arm/arm.md (one_cmpldi2): Rename to ... (one_cmpldi2_core): ... this, and modify it to prevent it being used for NEON. (one_cmpldi2): New define_expand. * config/arm/neon.md (one_cmpldi2_neon): New define_insn. --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4199,10 +4199,16 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)" "") -(define_insn_and_split "one_cmpldi2" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") - (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))] +(define_expand "one_cmpldi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (not:DI (match_operand:DI 1 "s_register_operand" "")))] "TARGET_32BIT" + "") + +(define_insn_and_split "*one_cmpldi2_core" + [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r") + (not:DI (match_operand:DI 1 "arm_general_register_operand" "0,r")))] + "TARGET_32BIT && !TARGET_NEON" "#" "TARGET_32BIT && reload_completed" [(set (match_dup 0) (not:SI (match_dup 1))) --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -896,6 +896,20 @@ [(set_attr "neon_type" "neon_int_1")] ) +(define_insn "*one_cmpldi2_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w") + (not:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w")))] + "TARGET_NEON" + "@ + vmvn\t%P0, %P1 + # + # + vmvn\t%P0, %P1" + [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") + (set_attr "length" "*,8,8,*") + (set_attr "arch" "nota8,*,*,onlya8")] +) + (define_insn "abs2" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]