From patchwork Fri Mar 11 14:48:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 507 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:43:12 -0000 Delivered-To: patches@linaro.org Received: by 10.224.67.207 with SMTP id s15cs61407qai; Fri, 11 Mar 2011 06:49:22 -0800 (PST) Received: by 10.227.153.145 with SMTP id k17mr8377501wbw.18.1299854961765; Fri, 11 Mar 2011 06:49:21 -0800 (PST) Received: from mail-ww0-f42.google.com (mail-ww0-f42.google.com [74.125.82.42]) by mx.google.com with ESMTPS id s28si8254418weq.80.2011.03.11.06.49.21 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Mar 2011 06:49:21 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.42 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=74.125.82.42; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.42 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by wwi17 with SMTP id 17so2660365wwi.1 for ; Fri, 11 Mar 2011 06:49:21 -0800 (PST) Received: by 10.227.130.96 with SMTP id r32mr8399580wbs.67.1299854918905; Fri, 11 Mar 2011 06:48:38 -0800 (PST) Received: from [192.168.32.36] (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id y29sm3436240wbd.22.2011.03.11.06.48.38 (version=SSLv3 cipher=OTHER); Fri, 11 Mar 2011 06:48:38 -0800 (PST) Message-ID: <4D7A3645.3070500@linaro.org> Date: Fri, 11 Mar 2011 14:48:37 +0000 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.14) Gecko/20110223 Thunderbird/3.1.8 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org CC: patches@linaro.org Subject: [Patch ARM] Fix PR47688 Hi, This patch fixes PR47688 which is a regression from gcc 4.4 and which ends up fixing https://bugs.launchpad.net/gcc-linaro/+bug/730440. The change is essentially in the punctuation character to only print out the lower 16 bits of the constant. I'll commit this into trunk and backport this to 4.5 branch once testing completes. A bootstrap of trunk for C, C++ and Fortran in Thumb2 has already completed and regression tests are on. Cheers Ramana 2011-03-10 Ramana Radhakrishnan PR target/47668 gcc/ * config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c' in the output template. gcc/testsuite/ * gcc.target/arm/pr47688.c: New. --- Ramana Radhakrishnan Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 170820) +++ gcc/config/arm/arm.md (working copy) @@ -10580,13 +10580,15 @@ [(set_attr "conds" "clob")] ) +;; We only care about the lower 16 bits of the constant +;; being inserted into the upper 16 bits of the register. (define_insn "*arm_movtas_ze" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") (const_int 16) (const_int 16)) (match_operand:SI 1 "const_int_operand" ""))] "arm_arch_thumb2" - "movt%?\t%0, %c1" + "movt%?\t%0, %L1" [(set_attr "predicable" "yes") (set_attr "length" "4")] ) --- /dev/null 2011-03-10 09:33:21.341560001 +0000 +++ ./gcc/testsuite/gcc.target/arm/pr47688.c 2011-03-10 15:46:16.197181998 +0000 @@ -0,0 +1,26 @@ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-final { scan-assembler-not "-32768" } } */ + +typedef union +{ + unsigned long int u_32_value; + struct + { + unsigned short int u_16_value_0; + unsigned short int u_16_value_1; + } u_16_values; +} my_union; + + +unsigned long int Test(const unsigned short int wXe) +{ + my_union dwCalcVal; + + dwCalcVal.u_16_values.u_16_value_0=wXe; + dwCalcVal.u_16_values.u_16_value_1=0x8000u; + + dwCalcVal.u_32_value /=3; + + return (dwCalcVal.u_32_value); +}