From patchwork Fri Oct 21 08:30:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiong Wang X-Patchwork-Id: 78608 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp1180366qge; Fri, 21 Oct 2016 01:30:38 -0700 (PDT) X-Received: by 10.98.89.73 with SMTP id n70mr9436352pfb.82.1477038638000; Fri, 21 Oct 2016 01:30:38 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id ze7si1403301pac.102.2016.10.21.01.30.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Oct 2016 01:30:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-439201-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-439201-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-439201-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=OkDUMhEEA28y4rOkEjZ6wp2BLunihw3nIBQJsEhXZj9Pefale6 szl2Z3aMiw//RP5A/SrzzZKnUeUfVSSpkp7kLlhCgYZi9x2jjnzfBEOFph7CCVpB f5/kfBbR0czBc/Qv56j14GuaRkc93vxubm/HzmPKsb6gs2mMg6+7P0PGA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; s= default; bh=UIFA6FQwcC+Yh7jkxYeDEeEuUCU=; b=MHYJMgg05jTO7yJfslBw wArpfvRQ0ZRvBX/ew0Rnlp7Debc/wfyhPQiDp/nfEUV7bbc61y+eyol4/MeqVzsr YbGnXkf86ZMsjvo0f419LATxnZRk2plJ5djTOX4veCvwI5+RgAnJp5oGYmP9LgkE MaJpVPg24QPypcG9u4H4WrE= Received: (qmail 66360 invoked by alias); 21 Oct 2016 08:30:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 66343 invoked by uid 89); 21 Oct 2016 08:30:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=val_, grouped, 30417, elem X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 21 Oct 2016 08:30:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D6506C16; Fri, 21 Oct 2016 01:30:04 -0700 (PDT) Received: from [10.2.206.198] (e104437-lin.cambridge.arm.com [10.2.206.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 43FD43F318; Fri, 21 Oct 2016 01:30:04 -0700 (PDT) To: gcc-patches Cc: Jakub Jelinek , Jason Merrill From: Jiong Wang Subject: [gcc] Enable DW_OP_VAL_EXPRESSION support in dwarf module Message-ID: <3849486f-84ee-31ad-e01c-93dcdb8ca1fa@foss.arm.com> Date: Fri, 21 Oct 2016 09:30:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 X-IsSubscribed: yes Currently, GCC only support DW_OP_EXPRESSION in dwarf module, this patch extend the support to DW_OP_VAL_EXPRESSION which share the same code mostly the same code with DW_OP_EXPRESSION. Meanwhile the existed dwarf expression parser only allows expressions which can be represented using GCC RTL. If one operation doesn't have a correspondent GCC RTL operator, then there is no way to attach that information in reg-note. This patch extends the current dwarf expression support to unlimited number of operations by using PARALLEL, and unlimited type of operations by using UNSPEC. All DW_OP_* of the expression are grouped together inside the PARALLEL, and those operations which don't have RTL mapping are wrapped by UNSPEC. The parsing algorithm is simply something like: foreach elem inside PARALLEL if (UNSPEC) { dw_op_code = INTVAL (XVECEXP (elem, 0, 0)); oprnd1 = INTVAL (XVECEXP (elem, 0, 1)); oprnd2 = INTVAL (XVECEXP (elem, 0, 2)); } else call standard RTL parser. Any comments on the approach? Thanks. gcc/ 2016-10-20 Jiong Wang * reg-notes.def (CFA_VAL_EXPRESSION): New entry. * dwarf2cfi.c (dwarf2out_frame_debug_cfa_val_expression): New function. (dwarf2out_frame_debug): Support REG_CFA_VAL_EXPRESSION. (output_cfa_loc): Support DW_CFA_val_expression. (output_cfa_loc_raw): Likewise. (output_cfi): Likewise. (output_cfi_directive): Likewise. * dwarf2out.c (dw_cfi_oprnd1_desc): Support DW_CFA_val_expression. (dw_cfi_oprnd2_desc): Likewise. (mem_loc_descriptor): Recognize new pattern generated for value expression. diff --git a/gcc/dwarf2cfi.c b/gcc/dwarf2cfi.c index 6491d5aaf4c4a21241cc718bfff1016f6d149951..b8c88fbae1df80a2664a414d8ae016a5343bf435 100644 --- a/gcc/dwarf2cfi.c +++ b/gcc/dwarf2cfi.c @@ -1235,7 +1235,7 @@ dwarf2out_frame_debug_cfa_register (rtx set) reg_save (sregno, dregno, 0); } -/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */ +/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */ static void dwarf2out_frame_debug_cfa_expression (rtx set) @@ -1267,6 +1267,29 @@ dwarf2out_frame_debug_cfa_expression (rtx set) update_row_reg_save (cur_row, regno, cfi); } +/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_VAL_EXPRESSION + note. */ + +static void +dwarf2out_frame_debug_cfa_val_expression (rtx set) +{ + rtx dest = SET_DEST (set); + gcc_assert (REG_P (dest)); + + rtx span = targetm.dwarf_register_span (dest); + gcc_assert (!span); + + rtx src = SET_SRC (set); + dw_cfi_ref cfi = new_cfi (); + cfi->dw_cfi_opc = DW_CFA_val_expression; + cfi->dw_cfi_oprnd1.dw_cfi_reg_num = dwf_regno (dest); + cfi->dw_cfi_oprnd2.dw_cfi_loc + = mem_loc_descriptor (src, GET_MODE (src), + GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); + add_cfi (cfi); + update_row_reg_save (cur_row, dwf_regno (dest), cfi); +} + /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */ static void @@ -2033,10 +2056,16 @@ dwarf2out_frame_debug (rtx_insn *insn) break; case REG_CFA_EXPRESSION: + case REG_CFA_VAL_EXPRESSION: n = XEXP (note, 0); if (n == NULL) n = single_set (insn); - dwarf2out_frame_debug_cfa_expression (n); + + if (REG_NOTE_KIND (note) == REG_CFA_EXPRESSION) + dwarf2out_frame_debug_cfa_expression (n); + else + dwarf2out_frame_debug_cfa_val_expression (n); + handled_one = true; break; @@ -3015,7 +3044,8 @@ output_cfa_loc (dw_cfi_ref cfi, int for_eh) dw_loc_descr_ref loc; unsigned long size; - if (cfi->dw_cfi_opc == DW_CFA_expression) + if (cfi->dw_cfi_opc == DW_CFA_expression + || cfi->dw_cfi_opc == DW_CFA_val_expression) { unsigned r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); @@ -3041,7 +3071,8 @@ output_cfa_loc_raw (dw_cfi_ref cfi) dw_loc_descr_ref loc; unsigned long size; - if (cfi->dw_cfi_opc == DW_CFA_expression) + if (cfi->dw_cfi_opc == DW_CFA_expression + || cfi->dw_cfi_opc == DW_CFA_val_expression) { unsigned r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); @@ -3188,6 +3219,7 @@ output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh) case DW_CFA_def_cfa_expression: case DW_CFA_expression: + case DW_CFA_val_expression: output_cfa_loc (cfi, for_eh); break; @@ -3302,16 +3334,13 @@ output_cfi_directive (FILE *f, dw_cfi_ref cfi) break; case DW_CFA_def_cfa_expression: - if (f != asm_out_file) - { - fprintf (f, "\t.cfi_def_cfa_expression ...\n"); - break; - } - /* FALLTHRU */ case DW_CFA_expression: + case DW_CFA_val_expression: if (f != asm_out_file) { - fprintf (f, "\t.cfi_cfa_expression ...\n"); + fprintf (f, "\t.cfi_%scfa_%sexpression ...\n", + cfi->dw_cfi_opc == DW_CFA_def_cfa_expression ? "def_" : "", + cfi->dw_cfi_opc == DW_CFA_val_expression ? "val_" : ""); break; } fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc); diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 4a3df339df2c6a6816ac8b8dbdb2466a7492c592..525abccd64d88ec0f3ba4ed59508879748106625 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -518,6 +518,7 @@ dw_cfi_oprnd1_desc (enum dwarf_call_frame_info cfi) case DW_CFA_def_cfa_register: case DW_CFA_register: case DW_CFA_expression: + case DW_CFA_val_expression: return dw_cfi_oprnd_reg_num; case DW_CFA_def_cfa_offset: @@ -551,6 +552,7 @@ dw_cfi_oprnd2_desc (enum dwarf_call_frame_info cfi) return dw_cfi_oprnd_reg_num; case DW_CFA_expression: + case DW_CFA_val_expression: return dw_cfi_oprnd_loc; default: @@ -14236,6 +14238,59 @@ mem_loc_descriptor (rtx rtl, machine_mode mode, resolve_one_addr (&rtl); goto symref; + /* RTL sequences inside PARALLEL are raw expression representation. + + mem_loc_descriptor can be used to build generic DWARF expressions for + DW_CFA_expression ad DW_CFA_val_expression where the expression may can + not be represented using normal RTL sequences. In this case, group all + expression operations (DW_OP_*) inside a PARALLEL. For those DW_OP which + doesn't have RTL mapping, wrap it using UNSPEC. The logic for parsing + PARALLEL sequences is: + + foreach elem inside PARALLEL + if (UNSPEC) + dw_op = UNSPEC elem 0 (the DWARF operation code) + oprnd1 = UNSPEC elem 1 + oprnd2 = UNSPEC elem 2 + else + call standard RTL parser (recursive call of mem_loc_descriptor) */ + case PARALLEL: + { + int index = 0; + dw_loc_descr_ref exp_result = NULL; + + for (; index < XVECLEN (rtl, 0); index++) + { + rtx elem = XVECEXP (rtl, 0, index); + if (GET_CODE (elem) == UNSPEC) + { + /* Each DWARF operation should always contain two operands, for + those operands not used, const0_rtx is passed. Plus the + operation code itself, there will be three elements for each + DWARF operation description UNSPEC. */ + gcc_assert (XVECLEN (elem, 0) == 3); + + HOST_WIDE_INT dw_op = INTVAL (XVECEXP (elem, 0, 0)); + HOST_WIDE_INT oprnd1 = INTVAL (XVECEXP (elem, 0, 1)); + HOST_WIDE_INT oprnd2 = INTVAL (XVECEXP (elem, 0, 2)); + exp_result = + new_loc_descr ((enum dwarf_location_atom) dw_op, oprnd1, + oprnd2); + } + else + exp_result = + mem_loc_descriptor (elem, mode, mem_mode, + VAR_INIT_STATUS_INITIALIZED); + + if (!mem_loc_result) + mem_loc_result = exp_result; + else + add_loc_descr (&mem_loc_result, exp_result); + } + + break; + } + default: if (flag_checking) { diff --git a/gcc/reg-notes.def b/gcc/reg-notes.def index 5374169b9a417d3695b685bfce2b44ff5d8c89e1..962dbb8007e5150d733344dd5a75495d9adf6a79 100644 --- a/gcc/reg-notes.def +++ b/gcc/reg-notes.def @@ -149,6 +149,11 @@ REG_NOTE (CFA_REGISTER) store of a register to an arbitrary (non-validated) memory address. */ REG_NOTE (CFA_EXPRESSION) +/* Attached to insns that are RTX_FRAME_RELATED_P, but are too complex + for FRAME_RELATED_EXPR intuition. The DWARF expression computes the value of + the given register. */ +REG_NOTE (CFA_VAL_EXPRESSION) + /* Attached to insns that are RTX_FRAME_RELATED_P, with the information that this is a restore operation, i.e. will result in DW_CFA_restore or the like. Either the attached rtx, or the destination of the insn's