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[209.132.180.131]) by mx.google.com with ESMTPS id b8si10557456pgn.82.2016.10.23.13.32.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 23 Oct 2016 13:32:43 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-439334-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-439334-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-439334-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=q4AcSpjrmpgh+6+m Fhp5OKCq3DmIhuQ6/NjGbajnWFEClrMTHayHulCb0LAZdtlgXPmym6w8HWf2NENc 6MXm6QomJS7j3uYL7bPIQu39CsP/CH/1Tqzm62M0KAnBO7n42tntXqpfOiW6On49 XYIfwzIwI8BYT6zwfMZPRXVkX40= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=0iTMqVpVtWN3XGl236CqPf 5bpO4=; b=GGY8kYfHNEvRgdkchEcKzTgwxI/fAUq2XtEFD29TqfUcNMRPcquf18 +R6kie/wdQZwZHQv3mvCtueybKQYH8L1z1eMdLBbmQJh62i7pxp6NdcHaHpWWAtH I4rO36vrBECZlc9QvMpK7xbFZAE/PEYtWqkBRt0Tg28aORk2wPT5E= Received: (qmail 28194 invoked by alias); 23 Oct 2016 20:32:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28180 invoked by uid 89); 23 Oct 2016 20:32:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.5 required=5.0 tests=AWL, BAYES_05, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=ew, eW, const_string, canonical X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 23 Oct 2016 20:32:14 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id D912C812EA for ; Sun, 23 Oct 2016 22:32:11 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JA90h4Aotom6 for ; Sun, 23 Oct 2016 22:32:11 +0200 (CEST) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id A184A812E9 for ; Sun, 23 Oct 2016 22:32:11 +0200 (CEST) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Cosmetic fixes for v3pipe attribute Date: Sun, 23 Oct 2016 22:32:10 +0200 Message-ID: <3544737.tFCVxnb33r@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-42-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 Tested on SPARC/Solaris, applied on the mainline and 6 branch. 2016-10-23 Eric Botcazou * config/sparc/sparc.md (cpu_feature): Minor tweak. (enabled): Likewise. (movsi_insn, movdi_insn_sp32, movdi_insn_sp64, movsf_insn, movdf_insn_sp32, movdf_insn_sp64, zero_extendsidi2_insn_sp64, sign_extendsidi2_insn, mov_insn, mov_insn_sp64, mov_insn_sp32, not_, nand_vis, _not1_vi, _not2_vis, one_cmpl2, fcmp, pdistn_vis): Likewise. -- Eric Botcazou Index: config/sparc/sparc.md =================================================================== --- config/sparc/sparc.md (revision 241437) +++ config/sparc/sparc.md (working copy) @@ -253,12 +253,13 @@ (define_attr "isa" "v7,v8,v9,sparclet" (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")] (const_string "v7")))) -(define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4" (const_string "none")) +(define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4" + (const_string "none")) (define_attr "enabled" "" (cond [(eq_attr "cpu_feature" "none") (const_int 1) (eq_attr "cpu_feature" "fpu") (symbol_ref "TARGET_FPU") - (eq_attr "cpu_feature" "fpunotv9") (symbol_ref "TARGET_FPU && ! TARGET_V9") + (eq_attr "cpu_feature" "fpunotv9") (symbol_ref "TARGET_FPU && !TARGET_V9") (eq_attr "cpu_feature" "v9") (symbol_ref "TARGET_V9") (eq_attr "cpu_feature" "vis") (symbol_ref "TARGET_VIS") (eq_attr "cpu_feature" "vis3") (symbol_ref "TARGET_VIS3") @@ -483,8 +484,7 @@ (define_attr "in_branch_delay" "false,tr (const_string "true") ] (const_string "false"))) -;; True if the instruction executes in the V3 pipeline, in M7 and -;; later processors. +;; True if the instruction executes in the V3 pipeline, in M7 and later processors. (define_attr "v3pipe" "false,true" (const_string "false")) (define_delay (eq_attr "type" "call") @@ -1559,8 +1559,8 @@ (define_insn "*movsi_insn" fzeros\t%0 fones\t%0" [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl") - (set_attr "v3pipe" "*,*,*,*,true,true,*,*,*,true,true") - (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")]) + (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis") + (set_attr "v3pipe" "*,*,*,*,true,true,*,*,*,true,true")]) (define_insn "*movsi_lo_sum" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1725,10 +1725,10 @@ (define_insn "*movdi_insn_sp32" fzero\t%0 fone\t%0" [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,*,*,*,fpload,fpstore,visl,visl") - (set_attr "v3pipe" "false, false, false, false,false,false,false,false,false,false,false,false,false,false,false,false,false,false, true, true") (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,2,2,2,*,*,*,*") (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double") - (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")]) + (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis") + (set_attr "v3pipe" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,true,true")]) (define_insn "*movdi_insn_sp64" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, r,*e,?*e,?*e,?W,b,b") @@ -1749,9 +1749,9 @@ (define_insn "*movdi_insn_sp64" fzero\t%0 fone\t%0" [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl") - (set_attr "v3pipe" "*, *, *, *, *, *, *, *, *, true, true") (set_attr "fptype" "*,*,*,*,*,*,double,*,*,double,double") - (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")]) + (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis") + (set_attr "v3pipe" "*,*,*,*,*,*,*,*,*,true,true")]) (define_expand "movdi_pic_label_ref" [(set (match_dup 3) (high:DI @@ -2313,8 +2313,8 @@ (define_insn "*movsf_insn" } } [(set_attr "type" "visl,visl,fpmove,*,*,*,vismv,vismv,fpload,load,fpstore,store") - (set_attr "v3pipe" "true, true, *, *, *, *, true, true, *, *, *, *") - (set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*")]) + (set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*") + (set_attr "v3pipe" "true,true,*,*,*,*,true,true,*,*,*,*")]) ;; The following 3 patterns build SFmode constants in integer registers. @@ -2382,10 +2382,10 @@ (define_insn "*movdf_insn_sp32" # #" [(set_attr "type" "visl,visl,fpmove,*,*,*,fpload,store,fpstore,load,store,*,*,*,*") - (set_attr "v3pipe" "true, true, *, *, *, *, *, *, *, *, *, *, *, *, *") (set_attr "length" "*,*,*,2,2,2,*,*,*,*,*,2,2,2,2") (set_attr "fptype" "double,double,double,*,*,*,*,*,*,*,*,*,*,*,*") - (set_attr "cpu_feature" "vis,vis,v9,fpunotv9,vis3,vis3,fpu,v9,fpu,*,*,fpu,*,*,fpu")]) + (set_attr "cpu_feature" "vis,vis,v9,fpunotv9,vis3,vis3,fpu,v9,fpu,*,*,fpu,*,*,fpu") + (set_attr "v3pipe" "true,true,*,*,*,*,*,*,*,*,*,*,*,*,*")]) (define_insn "*movdf_insn_sp64" [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,*r, e, e,W, *r,*r, m,*r") @@ -2406,10 +2406,10 @@ (define_insn "*movdf_insn_sp64" stx\t%r1, %0 #" [(set_attr "type" "visl,visl,fpmove,vismv,vismv,load,store,*,load,store,*") - (set_attr "v3pipe" "true, true, *, *, *, *, *, *, *, *, *") (set_attr "length" "*,*,*,*,*,*,*,*,*,*,2") (set_attr "fptype" "double,double,double,double,double,*,*,*,*,*,*") - (set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*")]) + (set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*") + (set_attr "v3pipe" "true,true,*,*,*,*,*,*,*,*,*")]) ;; This pattern builds DFmode constants in integer registers. (define_split @@ -3088,8 +3088,8 @@ (define_insn "*zero_extendsidi2_insn_sp6 lduw\t%1, %0 movstouw\t%1, %0" [(set_attr "type" "shift,load,*") - (set_attr "v3pipe" "*,*,true") - (set_attr "cpu_feature" "*,*,vis3")]) + (set_attr "cpu_feature" "*,*,vis3") + (set_attr "v3pipe" "*,*,true")]) (define_insn_and_split "*zero_extendsidi2_insn_sp32" [(set (match_operand:DI 0 "register_operand" "=r") @@ -3403,9 +3403,9 @@ (define_insn "*sign_extendsidi2_insn" ldsw\t%1, %0 movstosw\t%1, %0" [(set_attr "type" "shift,sload,*") - (set_attr "v3pipe" "*,*,true") (set_attr "us3load_type" "*,3cycle,*") - (set_attr "cpu_feature" "*,*,vis3")]) + (set_attr "cpu_feature" "*,*,vis3") + (set_attr "v3pipe" "*,*,true")]) ;; Special pattern for optimizing bit-field compares. This is needed @@ -8519,7 +8519,8 @@ (define_mode_iterator VM32 [V1SI V2HI V4 (define_mode_iterator VM64 [V1DI V2SI V4HI V8QI]) (define_mode_iterator VMALL [V1SI V2HI V4QI V1DI V2SI V4HI V8QI]) -(define_mode_attr vbits [(V2SI "32") (V4HI "16") (V1SI "32s") (V2HI "16s") (V8QI "8")]) +(define_mode_attr vbits [(V2SI "32") (V4HI "16") (V1SI "32s") (V2HI "16s") + (V8QI "8")]) (define_mode_attr vconstr [(V1SI "f") (V2HI "f") (V4QI "f") (V1DI "e") (V2SI "e") (V4HI "e") (V8QI "e")]) (define_mode_attr vfptype [(V1SI "single") (V2HI "single") (V4QI "single") @@ -8554,8 +8555,8 @@ (define_insn "*mov_insn" movstouw\t%1, %0 movwtos\t%1, %0" [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,*,vismv,vismv") - (set_attr "v3pipe" "true,true,true,false,false,false,false,false,false,true,true") - (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")]) + (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3") + (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,true,true")]) (define_insn "*mov_insn_sp64" [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,e,m,m,*r, m,*r, e,*r") @@ -8577,8 +8578,8 @@ (define_insn "*mov_insn_sp64" movxtod\t%1, %0 mov\t%1, %0" [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,vismv,vismv,*") - (set_attr "v3pipe" "true, true, true, false, false, false, false, false, false, false, false") - (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")]) + (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*") + (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,*,*")]) (define_insn "*mov_insn_sp32" [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,T, o,*r") @@ -8601,9 +8602,9 @@ (define_insn "*mov_insn_sp32" # #" [(set_attr "type" "visl,visl,vismv,*,*,fpload,fpstore,store,load,store,*,*") - (set_attr "v3pipe" "true, true, true, false, false, false, false, false, false, false, false, false") (set_attr "length" "*,*,*,2,2,*,*,*,*,*,2,2") - (set_attr "cpu_feature" "vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*")]) + (set_attr "cpu_feature" "vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*") + (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,*,*,*")]) (define_split [(set (match_operand:VM64 0 "memory_operand" "") @@ -8698,8 +8699,8 @@ (define_insn "3" "TARGET_VIS" "f\t%1, %2, %0" [(set_attr "type" "visl") - (set_attr "v3pipe" "true") - (set_attr "fptype" "")]) + (set_attr "fptype" "") + (set_attr "v3pipe" "true")]) (define_insn "*not_3" [(set (match_operand:VL 0 "register_operand" "=") @@ -8708,8 +8709,8 @@ (define_insn "*not_3" "TARGET_VIS" "f\t%1, %2, %0" [(set_attr "type" "visl") - (set_attr "v3pipe" "true") - (set_attr "fptype" "")]) + (set_attr "fptype" "") + (set_attr "v3pipe" "true")]) ;; (ior (not (op1)) (not (op2))) is the canonical form of NAND. (define_insn "*nand_vis" @@ -8719,8 +8720,8 @@ (define_insn "*nand_vis" "TARGET_VIS" "fnand\t%1, %2, %0" [(set_attr "type" "visl") - (set_attr "v3pipe" "true") - (set_attr "fptype" "")]) + (set_attr "fptype" "") + (set_attr "v3pipe" "true")]) (define_code_iterator vlnotop [ior and]) @@ -8731,8 +8732,8 @@ (define_insn "*_not1_vis" "TARGET_VIS" "fnot1\t%1, %2, %0" [(set_attr "type" "visl") - (set_attr "v3pipe" "true") - (set_attr "fptype" "")]) + (set_attr "fptype" "") + (set_attr "v3pipe" "true")]) (define_insn "*_not2_vis" [(set (match_operand:VL 0 "register_operand" "=") @@ -8741,8 +8742,8 @@ (define_insn "*_not2_vis" "TARGET_VIS" "fnot2\t%1, %2, %0" [(set_attr "type" "visl") - (set_attr "v3pipe" "true") - (set_attr "fptype" "")]) + (set_attr "fptype" "") + (set_attr "v3pipe" "true")]) (define_insn "one_cmpl2" [(set (match_operand:VL 0 "register_operand" "=") @@ -8750,8 +8751,8 @@ (define_insn "one_cmpl2" "TARGET_VIS" "fnot1\t%1, %0" [(set_attr "type" "visl") - (set_attr "v3pipe" "true") - (set_attr "fptype" "")]) + (set_attr "fptype" "") + (set_attr "v3pipe" "true")]) ;; Hard to generate VIS instructions. We have builtins for these. @@ -9117,8 +9118,8 @@ (define_insn "fcmp

\t%1, %2, %0" [(set_attr "type" "visl") - (set_attr "v3pipe" "true") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "v3pipe" "true")]) (define_insn "fpcmp8_vis" [(set (match_operand:P 0 "register_operand" "=r") @@ -9375,8 +9376,8 @@ (define_insn "pdistn_vis" "TARGET_VIS3" "pdistn\t%1, %2, %0" [(set_attr "type" "pdistn") - (set_attr "v3pipe" "true") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "v3pipe" "true")]) (define_insn "fmean16_vis" [(set (match_operand:V4HI 0 "register_operand" "=e")