| Message ID | 20191114100716.28827-2-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show
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[37.158.56.184]) by smtp.gmail.com with ESMTPSA id x26sm5359539wmc.14.2019.11.14.02.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 02:07:30 -0800 (PST) From: Richard Henderson <richard.henderson@linaro.org> To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH v2 1/6] aarch64: Add "c" constraint Date: Thu, 14 Nov 2019 11:07:11 +0100 Message-Id: <20191114100716.28827-2-richard.henderson@linaro.org> In-Reply-To: <20191114100716.28827-1-richard.henderson@linaro.org> References: <20191114100716.28827-1-richard.henderson@linaro.org> |
| Series |
Implement asm flag outputs for arm + aarch64
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expand
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diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index d0c3dd5bc1f..b9e5d13e851 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -39,6 +39,10 @@ (define_register_constraint "y" "FP_LO8_REGS" "Floating point and SIMD vector registers V0 - V7.") +(define_constraint "c" + "@internal The condition code register." + (match_operand 0 "cc_register")) + (define_constraint "I" "A constant that can be used with an ADD operation." (and (match_code "const_int")