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[213.99.162.212]) by smtp.gmail.com with ESMTPSA id 19sm8046565wrc.47.2019.11.08.02.54.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 02:54:22 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, richard.sandiford@arm.com, marcus.shawcroft@arm.com, kyrylo.tkachov@arm.com Subject: [PATCH 1/6] aarch64: Add "c" constraint Date: Fri, 8 Nov 2019 11:54:03 +0100 Message-Id: <20191108105408.27584-2-richard.henderson@linaro.org> In-Reply-To: <20191108105408.27584-1-richard.henderson@linaro.org> References: <20191108105408.27584-1-richard.henderson@linaro.org> Mirror arm in letting "c" match the condition code register. * config/aarch64/constraints.md (c): New constraint. --- gcc/config/aarch64/constraints.md | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index d0c3dd5bc1f..b9e5d13e851 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -39,6 +39,10 @@ (define_register_constraint "y" "FP_LO8_REGS" "Floating point and SIMD vector registers V0 - V7.") +(define_constraint "c" + "@internal The condition code register." + (match_operand 0 "cc_register")) + (define_constraint "I" "A constant that can be used with an ADD operation." (and (match_code "const_int")