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[209.132.180.131]) by mx.google.com with ESMTPS id d58si4840635eda.62.2019.10.18.12.57.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Oct 2019 12:57:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-511323-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=K1JDKV4C; spf=pass (google.com: domain of gcc-patches-return-511323-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-511323-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=F7gsbJOzCX0NjG/T GwW8sB7V/WNsJV24H1zQdAIJaWPWPDKQPE+vCDqZK29Wo4fuOvYCPOtuR1Qr9mJp 1iNMPZqIYXvWcpPeNLj6Q1ztxJ/91WVP0im0o8QB6MWYmRgcLTS40qitqAodKUN6 w+DnmCl1cCzYkJD56nxpA9oZY4Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=yVHKZMIBdey38xM/uOqLKw y4Rww=; b=K1JDKV4CZigLOW+G81ENqxCXw/LWRsvZEj0X27/0Jdd1o8p6XVz6Nu Yqcmt7UHuVES/kEkFwnRBmmiyV6H2GaZTFB1+cDPGQwMk3wRXjAdJK6nApHeDBs4 5Tod2EG0VnEPpeMIGbwIBCfUQtUk/sosqJEUDroz30piOgcQ4s2R4= Received: (qmail 114604 invoked by alias); 18 Oct 2019 19:55:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 113028 invoked by uid 89); 18 Oct 2019 19:55:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.1 spammy=minmax X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (209.51.188.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Oct 2019 19:55:39 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLYLS-00055m-PU for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:32 -0400 Received: from [217.140.110.172] (port=42752 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1iLYLS-00054V-Go for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:30 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E719E1655; Fri, 18 Oct 2019 12:49:17 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 746793F6C4; Fri, 18 Oct 2019 12:49:17 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 08/29] [arm] Introduce arm_carry_operation Date: Fri, 18 Oct 2019 20:48:39 +0100 Message-Id: <20191018194900.34795-9-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.110.172 An earlier patch introduced arm_borrow_operation, this one introduces the carry variant, which is the same except that the logic of the carry-setting is inverted. Having done this we can now match more cases where the carry flag is propagated from comparisons with different modes without having to define even more patterns. A few small changes to the expand patterns are required to directly create the carry representation. The iterators LTUGEU is no-longer needed and removed, as is the code attribute 'cnb'. Finally, we fix a long-standing bug which was probably inert before: in Thumb2 a shift with ADC can only be by an immediate amount; register-specified shifts are not permitted. * config/arm/predicates.md (arm_carry_operation): New special predicate. * config/arm/iterators.md (LTUGEU): Delete iterator. (cnb): Delete code attribute. (optab): Delete ltu and geu elements. * config/arm/arm.md (addsi3_carryin): Renamed from addsi3_carryin_. Remove iterator and use arm_carry_operand. (add0si3_carryin): Similarly, but from add0si3_carryin_. (addsi3_carryin_alt2): Similarly, but from addsi3_carryin_alt2_. (addsi3_carryin_clobercc): Similarly. (addsi3_carryin_shift): Similarly. Do not allow register shifts in Thumb2 state. --- gcc/config/arm/arm.md | 36 ++++++++++++++++++++---------------- gcc/config/arm/iterators.md | 11 +---------- gcc/config/arm/predicates.md | 21 +++++++++++++++++++++ 3 files changed, 42 insertions(+), 26 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index f597a277c17..f53dbc27207 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -471,10 +471,12 @@ (define_expand "adddi3" hi_op2 = force_reg (SImode, hi_op2); emit_insn (gen_addsi3_compareC (lo_dest, lo_op1, lo_op2)); + rtx carry = gen_rtx_LTU (SImode, gen_rtx_REG (CC_Cmode, CC_REGNUM), + const0_rtx); if (hi_op2 == const0_rtx) - emit_insn (gen_add0si3_carryin_ltu (hi_dest, hi_op1)); + emit_insn (gen_add0si3_carryin (hi_dest, hi_op1, carry)); else - emit_insn (gen_addsi3_carryin_ltu (hi_dest, hi_op1, hi_op2)); + emit_insn (gen_addsi3_carryin (hi_dest, hi_op1, hi_op2, carry)); } if (lo_result != lo_dest) @@ -858,11 +860,11 @@ (define_insn "*compare_addsi2_op1" (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")] ) -(define_insn "addsi3_carryin_" +(define_insn "addsi3_carryin" [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r") (match_operand:SI 2 "arm_not_operand" "0,rI,K")) - (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))))] + (match_operand:SI 3 "arm_carry_operation" "")))] "TARGET_32BIT" "@ adc%?\\t%0, %1, %2 @@ -877,9 +879,9 @@ (define_insn "addsi3_carryin_" ) ;; Canonicalization of the above when the immediate is zero. -(define_insn "add0si3_carryin_" +(define_insn "add0si3_carryin" [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) + (plus:SI (match_operand:SI 2 "arm_carry_operation" "") (match_operand:SI 1 "arm_not_operand" "r")))] "TARGET_32BIT" "adc%?\\t%0, %1, #0" @@ -889,9 +891,9 @@ (define_insn "add0si3_carryin_" (set_attr "type" "adc_imm")] ) -(define_insn "*addsi3_carryin_alt2_" +(define_insn "*addsi3_carryin_alt2" [(set (match_operand:SI 0 "s_register_operand" "=l,r,r") - (plus:SI (plus:SI (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)) + (plus:SI (plus:SI (match_operand:SI 3 "arm_carry_operation" "") (match_operand:SI 1 "s_register_operand" "%l,r,r")) (match_operand:SI 2 "arm_not_operand" "l,rI,K")))] "TARGET_32BIT" @@ -907,28 +909,30 @@ (define_insn "*addsi3_carryin_alt2_" (set_attr "type" "adc_reg,adc_reg,adc_imm")] ) -(define_insn "*addsi3_carryin_shift_" - [(set (match_operand:SI 0 "s_register_operand" "=r") +(define_insn "*addsi3_carryin_shift" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (plus:SI (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "reg_or_int_operand" "rM")]) - (LTUGEU:SI (reg: CC_REGNUM) (const_int 0))) - (match_operand:SI 1 "s_register_operand" "r")))] + [(match_operand:SI 3 "s_register_operand" "r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r")]) + (match_operand:SI 5 "arm_carry_operation" "")) + (match_operand:SI 1 "s_register_operand" "r,r")))] "TARGET_32BIT" "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") + (set_attr "arch" "32,a") + (set_attr "shift" "3") (set_attr "predicable" "yes") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") (const_string "alu_shift_imm") (const_string "alu_shift_reg")))] ) -(define_insn "*addsi3_carryin_clobercc_" +(define_insn "*addsi3_carryin_clobercc" [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") (match_operand:SI 2 "arm_rhs_operand" "rI")) - (LTUGEU:SI (reg: CC_REGNUM) (const_int 0)))) + (match_operand:SI 3 "arm_carry_operation" ""))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" "adcs%?\\t%0, %1, %2" diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 8c9f7121951..77e1645083f 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -219,11 +219,6 @@ (define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) ;; Code iterators ;;---------------------------------------------------------------------------- -;; A list of condition codes used in compare instructions where -;; the carry flag from the addition is used instead of doing the -;; compare a second time. -(define_code_iterator LTUGEU [ltu geu]) - ;; The signed gt, ge comparisons (define_code_iterator GTGE [gt ge]) @@ -809,13 +804,9 @@ (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") (umax "u")]) -(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) - ;; Map rtl operator codes to optab names (define_code_attr optab - [(ltu "ltu") - (geu "geu") - (and "and") + [(and "and") (ior "ior") (xor "xor")]) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index e6766a97fc4..ed7495b69fc 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -356,6 +356,27 @@ (define_predicate "arm_comparison_operator_mode" (define_special_predicate "lt_ge_comparison_operator" (match_code "lt,ge")) +(define_special_predicate "arm_carry_operation" + (match_code "geu,ltu") + { + if (XEXP (op, 1) != const0_rtx) + return false; + + rtx op0 = XEXP (op, 0); + + if (!REG_P (op0) || REGNO (op0) != CC_REGNUM) + return false; + + machine_mode ccmode = GET_MODE (op0); + if (ccmode == CC_Cmode) + return GET_CODE (op) == LTU; + else if (ccmode == CCmode || ccmode == CC_RSBmode) + return GET_CODE (op) == GEU; + + return false; + } +) + ;; Match a "borrow" operation for use with SBC. The precise code will ;; depend on the form of the comparison. This is generally the inverse of ;; a carry operation, since the logic of SBC uses "not borrow" in it's