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[209.132.180.131]) by mx.google.com with ESMTPS id 17si3834649ejx.213.2019.10.18.13.00.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Oct 2019 13:00:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-511337-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=dXodZHC6; spf=pass (google.com: domain of gcc-patches-return-511337-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-511337-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=ZOvKA7jtvfdLRP1S qUSFim0a3EUbqY8bvxG+y7qAxsYOPZrbdaLBr8DuUDh7lFCaRbn5Zkiw0ntYG0pf uiBI20XdKohTeZ1hTtwoTY/PxuBj41te8gBLE1uDOFn0TNtYpCqhp5c1uaVDqGyy D0OU2B7r2MBcx/E/v38BEwmX8Vg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=slV7eUVSo12GJKIDpY7iss /a/DQ=; b=dXodZHC6gzrTi8y0mVIB7SlU0Q2JlSOj4qa19aBNl+HqDG1qxyCY9y qwiMdvMrorB2kbDbT8scKgG1WbMK5O0d4Ja4aV4jMwzLm6F1Ljo8HBH+yM/CPqFM cMMOpjrUTOCABu5SgRvbu0cyJtiW93NVHLvDNUObf2XfM4qwlSwyw= Received: (qmail 122143 invoked by alias); 18 Oct 2019 19:56:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115937 invoked by uid 89); 18 Oct 2019 19:55:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.1 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (209.51.188.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Oct 2019 19:55:49 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLYLd-0005AX-5H for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:42 -0400 Received: from [217.140.110.172] (port=42764 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1iLYLc-00055U-TV for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3F23B1650; Fri, 18 Oct 2019 12:49:17 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C0B7C3F6C4; Fri, 18 Oct 2019 12:49:16 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 07/29] [arm] Remove redundant DImode subtract patterns Date: Fri, 18 Oct 2019 20:48:38 +0100 Message-Id: <20191018194900.34795-8-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.110.172 Now that we early split DImode subtracts, the patterns to emit the original and to match zero-extend with subtraction or negation are no-longer useful. * config/arm/arm.md (arm_subdi3): Delete insn. (zextendsidi_negsi, negdi_extendsidi): Delete insn_and_split. --- gcc/config/arm/arm.md | 102 ------------------------------------------ 1 file changed, 102 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 99d931525f8..f597a277c17 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1161,18 +1161,6 @@ (define_expand "subdi3" " ) -(define_insn "*arm_subdi3" - [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r") - (minus:DI (match_operand:DI 1 "arm_general_register_operand" "0,r,0") - (match_operand:DI 2 "arm_general_register_operand" "r,0,0"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT" - "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" - [(set_attr "conds" "clob") - (set_attr "length" "8") - (set_attr "type" "multiple")] -) - (define_expand "subsi3" [(set (match_operand:SI 0 "s_register_operand") (minus:SI (match_operand:SI 1 "reg_or_int_operand") @@ -3866,96 +3854,6 @@ (define_expand "negdf2" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "") -(define_insn_and_split "*zextendsidi_negsi" - [(set (match_operand:DI 0 "s_register_operand" "=r") - (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))] - "TARGET_32BIT" - "#" - "" - [(set (match_dup 2) - (neg:SI (match_dup 1))) - (set (match_dup 3) - (const_int 0))] - { - operands[2] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[0]); - } - [(set_attr "length" "8") - (set_attr "type" "multiple")] -) - -;; Negate an extended 32-bit value. -(define_insn_and_split "*negdi_extendsidi" - [(set (match_operand:DI 0 "s_register_operand" "=l,r") - (neg:DI (sign_extend:DI - (match_operand:SI 1 "s_register_operand" "l,r")))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_32BIT" - "#" - "&& reload_completed" - [(const_int 0)] - { - rtx low = gen_lowpart (SImode, operands[0]); - rtx high = gen_highpart (SImode, operands[0]); - - if (reg_overlap_mentioned_p (low, operands[1])) - { - /* Input overlaps the low word of the output. Use: - asr Rhi, Rin, #31 - rsbs Rlo, Rin, #0 - rsc Rhi, Rhi, #0 (thumb2: sbc Rhi, Rhi, Rhi, lsl #1). */ - rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); - - emit_insn (gen_rtx_SET (high, - gen_rtx_ASHIFTRT (SImode, operands[1], - GEN_INT (31)))); - - emit_insn (gen_subsi3_compare (low, const0_rtx, operands[1])); - if (TARGET_ARM) - emit_insn (gen_rtx_SET (high, - gen_rtx_MINUS (SImode, - gen_rtx_MINUS (SImode, - const0_rtx, - high), - gen_rtx_LTU (SImode, - cc_reg, - const0_rtx)))); - else - { - rtx two_x = gen_rtx_ASHIFT (SImode, high, GEN_INT (1)); - emit_insn (gen_rtx_SET (high, - gen_rtx_MINUS (SImode, - gen_rtx_MINUS (SImode, - high, - two_x), - gen_rtx_LTU (SImode, - cc_reg, - const0_rtx)))); - } - } - else - { - /* No overlap, or overlap on high word. Use: - rsb Rlo, Rin, #0 - bic Rhi, Rlo, Rin - asr Rhi, Rhi, #31 - Flags not needed for this sequence. */ - emit_insn (gen_rtx_SET (low, gen_rtx_NEG (SImode, operands[1]))); - emit_insn (gen_rtx_SET (high, - gen_rtx_AND (SImode, - gen_rtx_NOT (SImode, operands[1]), - low))); - emit_insn (gen_rtx_SET (high, - gen_rtx_ASHIFTRT (SImode, high, - GEN_INT (31)))); - } - DONE; - } - [(set_attr "length" "12") - (set_attr "arch" "t2,*") - (set_attr "type" "multiple")] -) - ;; abssi2 doesn't really clobber the condition codes if a different register ;; is being set. To keep things simple, assume during rtl manipulations that ;; it does, but tell the final scan operator the truth. Similarly for