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[209.132.180.131]) by mx.google.com with ESMTPS id y54si4969322edb.217.2019.10.18.12.59.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Oct 2019 12:59:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-511332-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ILcX7YvJ; spf=pass (google.com: domain of gcc-patches-return-511332-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-511332-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=PoDY3VvoZpX5dSFk xrt2tJp0/vBkp0mKnYRfLJhZK8sRmvxMwjQDUlSO1I4PP3anFEOOMnl3yDFXxFnQ u3kmqSJJxlFfYDBN6ewXwlhQM/KWzwdpwG5aAhv1v2FjPa3v5/PYrZVHslZnuvET Iiefi8V7Ue13BwF2KJCZZiGpco4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=pjZcwv0YFOQeGQWIK36Hni hjyAY=; b=ILcX7YvJueoyKIVS8o/bIQytsWhXZ/FT+Ci5bVoQdGhQq1tzZlJqjx zYnfTN6+NV20AI+Sr/6NMY/4uOoSQlLTLfOs/p8+6cVqFNhGGfiA3r1LyxpJasWY s/z7vhKaT1NK+maBsVUXnEnTDXgB+EJf44LyobFAaMyDT6EhfJ00A= Received: (qmail 117569 invoked by alias); 18 Oct 2019 19:56:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115224 invoked by uid 89); 18 Oct 2019 19:55:47 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.1 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (209.51.188.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Oct 2019 19:55:45 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLYLd-0005BF-Or for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:42 -0400 Received: from [217.140.110.172] (port=42774 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1iLYLd-000563-Ft for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D8D26175D; Fri, 18 Oct 2019 12:49:26 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 661B23F6C4; Fri, 18 Oct 2019 12:49:26 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 21/29] [arm] Improve code generation for addvsi4. Date: Fri, 18 Oct 2019 20:48:52 +0100 Message-Id: <20191018194900.34795-22-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.110.172 Similar to the improvements for uaddvsi4, this patch improves the code generation for addvsi4 to handle immediates and to add alternatives that better target thumb2. To do this we separate out the expansion of uaddvsi4 from that of uaddvdi4 and then add an additional pattern to handle constants. Also, while doing this I've fixed the incorrect usage of NE instead of COMPARE in the generated RTL. * config/arm/arm.md (addv4): Delete. (addvsi4): New pattern. Handle immediate values that the architecture supports. (addvdi4): New pattern. (addsi3_compareV): Rename to ... (addsi3_compareV_reg): ... this. Add constraints for thumb2 variants and use COMPARE rather than NE. (addsi3_compareV_imm): New pattern. * config/arm/arm.c (arm_select_cc_mode): Return CC_Vmode for a signed-overflow check. --- gcc/config/arm/arm.c | 8 ++++++ gcc/config/arm/arm.md | 63 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 61 insertions(+), 10 deletions(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index eebbdc3d9c2..638c82df25f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -15411,6 +15411,14 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) || arm_borrow_operation (y, DImode))) return CC_Bmode; + if (GET_MODE (x) == DImode + && (op == EQ || op == NE) + && GET_CODE (x) == PLUS + && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND + && GET_CODE (y) == SIGN_EXTEND + && GET_CODE (XEXP (y, 0)) == PLUS) + return CC_Vmode; + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) return GET_MODE (x); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9f0e43571fd..b5214c79c35 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -488,14 +488,30 @@ (define_expand "adddi3" " ) -(define_expand "addv4" - [(match_operand:SIDI 0 "register_operand") - (match_operand:SIDI 1 "register_operand") - (match_operand:SIDI 2 "register_operand") +(define_expand "addvsi4" + [(match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_add_operand") (match_operand 3 "")] "TARGET_32BIT" { - emit_insn (gen_add3_compareV (operands[0], operands[1], operands[2])); + if (CONST_INT_P (operands[2])) + emit_insn (gen_addsi3_compareV_imm (operands[0], operands[1], operands[2])); + else + emit_insn (gen_addsi3_compareV_reg (operands[0], operands[1], operands[2])); + arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); + + DONE; +}) + +(define_expand "addvdi4" + [(match_operand:DI 0 "register_operand") + (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "register_operand") + (match_operand 3 "")] + "TARGET_32BIT" +{ + emit_insn (gen_adddi3_compareV (operands[0], operands[1], operands[2])); arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); DONE; @@ -770,21 +786,48 @@ (define_insn "adddi3_compareV" (set_attr "type" "multiple")] ) -(define_insn "addsi3_compareV" +(define_insn "addsi3_compareV_reg" [(set (reg:CC_V CC_REGNUM) - (ne:CC_V + (compare:CC_V (plus:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) + (sign_extend:DI (match_operand:SI 1 "register_operand" "%l,0,r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "l,r,r"))) (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2))))) - (set (match_operand:SI 0 "register_operand" "=r") + (set (match_operand:SI 0 "register_operand" "=l,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "adds%?\\t%0, %1, %2" [(set_attr "conds" "set") + (set_attr "arch" "t2,t2,*") + (set_attr "length" "2,2,4") (set_attr "type" "alus_sreg")] ) +(define_insn "addsi3_compareV_imm" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus:DI + (sign_extend:DI + (match_operand:SI 1 "register_operand" "l,0,l,0,r,r")) + (match_operand 2 "arm_addimm_operand" "Pd,Py,Px,Pw,I,L")) + (sign_extend:DI (plus:SI (match_dup 1) (match_dup 2))))) + (set (match_operand:SI 0 "register_operand" "=l,l,l,l,r,r") + (plus:SI (match_dup 1) (match_dup 2)))] + "TARGET_32BIT + && INTVAL (operands[2]) == ARM_SIGN_EXTEND (INTVAL (operands[2]))" + "@ + adds%?\\t%0, %1, %2 + adds%?\\t%0, %0, %2 + subs%?\\t%0, %1, #%n2 + subs%?\\t%0, %0, #%n2 + adds%?\\t%0, %1, %2 + subs%?\\t%0, %1, #%n2" + [(set_attr "conds" "set") + (set_attr "arch" "t2,t2,t2,t2,*,*") + (set_attr "length" "2,2,2,2,4,4") + (set_attr "type" "alus_imm")] +) + (define_insn "addsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV