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[209.132.180.131]) by mx.google.com with ESMTPS id p11si1794224pgm.551.2019.05.15.05.44.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 May 2019 05:44:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-500776-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=v1HGuRrp; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=loVJ70ua; spf=pass (google.com: domain of gcc-patches-return-500776-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-500776-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; q=dns; s=default; b=Y+z 7YrTu/8+8zjOlx0RT6e5MPCsHt9AbpCHTp8SRTi6Um/SrZLHmiZfFbzP75dTo5V+ CjeJkkZSK8MTXpUEAk7HgJxNK5XAFgK7YuhMje42Z2o04LBIBT9o6iCDvIfxb/O+ LWQUaZ0T3ctV9WiwmpOBHxTQwQN2mESBdlivAxV4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; s=default; bh=b3mLX048i 0bjNr80IpRLIxFI9io=; b=v1HGuRrppvZOfdmtK2zqSQ9sDn0C9oU0plGbpoQVM gELlUzlRLuwUdWlREmTSv8ABpDLdkqlubuXyWNrj+/MDueu8hYtvUQZ5/j8IJ60h sbQDe9ucXkR9q7aS9aP9plEeUS56OuA2Mwcmz4OnwN569ZgGOgarh/evh0KbOw93 yA= Received: (qmail 62757 invoked by alias); 15 May 2019 12:44:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61744 invoked by uid 89); 15 May 2019 12:44:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx07-00178001.pphosted.com Received: from mx08-00178001.pphosted.com (HELO mx07-00178001.pphosted.com) (91.207.212.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 15 May 2019 12:44:20 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4FCgRg9014582 for ; Wed, 15 May 2019 14:44:18 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=STMicroelectronics; bh=5vfvCIyle0VbCWOQhsim34krrpvizqGVN/gRkdLFHl8=; b=loVJ70uaUvwVWQwVWC/Kw/ZyXAaMlvTTEB8RC1FlnIJYWzekWrTi3MmYfPHOkZcbhbp3 2kQHO8niQptmH82Xpl0KmVdR1XmzcS31vFHAvNXjB+SU+ILU6RotJ5L63zAPuHOnwRJC PYcVjqZuI7YzKjtebVg5oDcyCjYfwujKj6Sx9kl4SrxiaA0Z87SAMkG1TOTUNIPksOQM etqYV6JDQ3Mf+4Dd9kfWuM25RvkyN7pgUDfELEIpJzVs21mGmW/x+aw6VCT62zwBmGEQ IIwAQVc6RQCAsDMkJGG/nvOvhtFB/RFK5l/j3T8PReNhs9kMm4lK3ihtJ1py3mUv3OqI oQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2sdn9g0t6p-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT) for ; Wed, 15 May 2019 14:44:18 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0E84D3A for ; Wed, 15 May 2019 12:44:17 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8907E2762 for ; Wed, 15 May 2019 12:44:17 +0000 (GMT) Received: from gnb.st.com (10.75.127.45) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 15 May 2019 14:44:16 +0200 From: Christophe Lyon To: Subject: [ARM/FDPIC v5 12/21] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp Date: Wed, 15 May 2019 14:39:37 +0200 Message-ID: <20190515124006.25840-13-christophe.lyon@st.com> In-Reply-To: <20190515124006.25840-1-christophe.lyon@st.com> References: <20190515124006.25840-1-christophe.lyon@st.com> MIME-Version: 1.0 X-IsSubscribed: yes We call __aeabi_read_tp() to get the thread pointer. Since this is a function call, we have to restore the FDPIC register afterwards. 2019-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_load_tp): Add FDPIC support. * config/arm/arm.md (load_tp_soft_fdpic): New pattern. (load_tp_soft): Disable in FDPIC mode. Change-Id: I1f6dfaee6260ecb453270f4971b3c5124317a186 -- 2.6.3 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5fc7a20..26f29c7 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8732,7 +8732,25 @@ arm_load_tp (rtx target) rtx tmp; - emit_insn (gen_load_tp_soft ()); + if (TARGET_FDPIC) + { + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); + + emit_insn (gen_load_tp_soft_fdpic ()); + + /* Restore r9. */ + XVECEXP (par, 0, 0) = gen_rtx_UNSPEC (VOIDmode, + gen_rtvec (2, fdpic_reg, + initial_fdpic_reg), + UNSPEC_PIC_RESTORE); + XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, initial_fdpic_reg); + XVECEXP (par, 0, 2) = gen_rtx_CLOBBER (VOIDmode, fdpic_reg); + emit_insn (par); + } + else + emit_insn (gen_load_tp_soft ()); tmp = gen_rtx_REG (SImode, R0_REGNUM); emit_move_insn (target, tmp); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9036255..0edcb1d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11759,12 +11759,25 @@ ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. +(define_insn "load_tp_soft_fdpic" + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) + (clobber (reg:SI 9)) + (clobber (reg:SI LR_REGNUM)) + (clobber (reg:SI IP_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_SOFT_TP && TARGET_FDPIC" + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob") + (set_attr "type" "branch")] +) + +;; Doesn't clobber R1-R3. Must use r0 for the first operand. (define_insn "load_tp_soft" [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) (clobber (reg:SI LR_REGNUM)) (clobber (reg:SI IP_REGNUM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_SOFT_TP" + "TARGET_SOFT_TP && !TARGET_FDPIC" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" [(set_attr "conds" "clob") (set_attr "type" "branch")]