From patchwork Wed Sep 26 05:03:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 147532 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp262136lji; Tue, 25 Sep 2018 22:04:52 -0700 (PDT) X-Google-Smtp-Source: ACcGV63GrVC9KQTyqOGszl7vUV2hee4hkhTkgwORjzJ8t1+dBW16LKrSmTwPU/uy4455tvU9S9F0 X-Received: by 2002:a62:6a01:: with SMTP id f1-v6mr4328507pfc.156.1537938292212; Tue, 25 Sep 2018 22:04:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537938292; cv=none; d=google.com; s=arc-20160816; b=VtoP/8KewwvOCWlkCzuABv9e7YGyww9e8Y/70vBUmwaHPodupEkmPi2avZyW4ypIuQ udrNIG5/7u4WGdmmZWM2awEyoiPmg78e48jDH21y899MGLbFrwy1KM+qFgBZ7fAAbHmx TSc/ofWakdR3IIzd1omEr7d6mwDWY8E1owIDW8mSzMLhDipO4kwm9fdp939PClrLygZ8 83x8gMfE6JGn6L+kq8v12oeFzX07DkDeQvZoAJLB1gVRLlBIRFIaV2+Z2eOdux72gnsW YSOsgAe9aIHLYKUVR0iy/SPF8X1BFnQoEItzzIs1F6p2qWnGi0iPVajGHUU4wqCKwMHN TA5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature; bh=6B03dof+teYsXIe2TnCXcd7CuBYOZp6d2Oce+2KGyRI=; b=X8wdyJd2Ea5M7GvvJnH0tDWz5UqyW4p7R1Czqm2iTCw0d3k+9hjt0i15pXKJTe3CCp DEOKq+hAnRUncVss44rbAiR3m90RDMdmLRG6bJGu5OgPiFIbE1ZAnBlZeSotm0UaocdP 1gKE3gzJAh3cludSeOgdb0/UvjRFHGNwa0FwHa6xNHu9lUzc4bh8zDcTu0oUHf4yW2bq KDEgRchzsyLCcsScEbmSbvWJYgbB/VyAoudAhA2UFvKc7uKFS5mYfWQGsiV7dgHbSNpZ 6r+66yag6lvbT6Lp/WqPAF715HChhuOmsCqyjnNEJGoZdGzp4xYMTNTwd5tDsUzgPZI1 7aHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=v3SX4Kzd; dkim=pass header.i=@gmail.com header.s=20161025 header.b=e197oVeE; spf=pass (google.com: domain of gcc-patches-return-486385-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-486385-patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id h3-v6si4356953plh.469.2018.09.25.22.04.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Sep 2018 22:04:52 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-486385-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=v3SX4Kzd; dkim=pass header.i=@gmail.com header.s=20161025 header.b=e197oVeE; spf=pass (google.com: domain of gcc-patches-return-486385-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-486385-patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=Pm1B6S4pYEJ33mtcs2H/rFjtx9gr2OLKWe2Qfh18nLUwslrlCuLRA p6iE9jVjUpxjg3GiiYmwqlWGVR2V8iRXXL0pxV0oNNNgKsUzLxvMOrpjOSpSVE4R Al0pPWzbGps4RxmTUaBCG2DduOg4H9OKeKgM0v4v9d3XHr4HL828Yg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=ZvWuG/APe5aRiX7FPVNITnJBMgE=; b=v3SX4KzddO4BMG+sftrh a3/EawQtRqnhCPMkR2M63TyFklioQ7OJmjIwr1YIn6QQBcWbBTMg8Lryn+ZRGjOI bbGk/Uf1wWzguaiCLfA+1w01t+LzSp5Ok11OgD0QnKCU7AMcDececQbZiIDSDMAj 9pNafJJ9vxmVKwRjLxeHe7Y= Received: (qmail 73581 invoked by alias); 26 Sep 2018 05:04:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73388 invoked by uid 89); 26 Sep 2018 05:04:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=alli, HX-Received:sk:c6-v6mr, HX-Received:7246 X-HELO: mail-pf1-f181.google.com Received: from mail-pf1-f181.google.com (HELO mail-pf1-f181.google.com) (209.85.210.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 26 Sep 2018 05:04:01 +0000 Received: by mail-pf1-f181.google.com with SMTP id a23-v6so5100675pfi.12 for ; Tue, 25 Sep 2018 22:04:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6B03dof+teYsXIe2TnCXcd7CuBYOZp6d2Oce+2KGyRI=; b=e197oVeE5iYJZcVjH0lbeIPdCLLBWQ/ShM7Rs0zM2m7x8gVtZrnU7st7fI33MDJJGv sQqQzFcNKj+yvkcpABPczcURycf2CCGH5XDosA8z1PxV+1qEipklJ1k0O/tPve+KuL82 8saZ9uM5MKbxDHRtiMps2CJdDjw9u3e2qW2WBzSx0nOzzybFgr1Rxoh7EreU62lE9GsE qvGdarB72FHlincXahSVXlxCHVKGKJ6nJ7ytCqBtLb4rNpX+6ILENuCTuyGKGqAtq0fa 7jbHbdgi75opvW5XaGlb5tS3TSKQ553kIyMc+6gNNLpUMCfl3P8psZqf8GHgFtsVqy3z kdcg== Return-Path: Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id j22-v6sm4954650pfh.45.2018.09.25.22.03.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 22:03:59 -0700 (PDT) From: rth7680@gmail.com To: gcc-patches@gcc.gnu.org Cc: ramana.radhakrishnan@arm.com, agraf@suse.de, matz@suse.de, Richard Henderson Subject: [PATCH, AArch64 03/11] aarch64: Improve swp generation Date: Tue, 25 Sep 2018 22:03:47 -0700 Message-Id: <20180926050355.32746-4-richard.henderson@linaro.org> In-Reply-To: <20180926050355.32746-1-richard.henderson@linaro.org> References: <20180926050355.32746-1-richard.henderson@linaro.org> From: Richard Henderson Allow zero as an input; fix constraints; avoid unnecessary split. * config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove. (aarch64_gen_atomic_ldop): Don't call it. * config/aarch64/atomics.md (atomic_exchange): Use aarch64_reg_or_zero. (aarch64_atomic_exchange): Likewise. (aarch64_atomic_exchange_lse): Remove split; remove & from operand 0; use aarch64_reg_or_zero for input; merge ... (@aarch64_atomic_swp): ... this and remove. --- gcc/config/aarch64/aarch64.c | 13 ---------- gcc/config/aarch64/atomics.md | 49 +++++++++++------------------------ 2 files changed, 15 insertions(+), 47 deletions(-) -- 2.17.1 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c0f2d296342..5e9a85be44c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -14401,15 +14401,6 @@ aarch64_emit_bic (machine_mode mode, rtx dst, rtx s1, rtx s2, int shift) emit_insn (gen (dst, s2, shift_rtx, s1)); } -/* Emit an atomic swap. */ - -static void -aarch64_emit_atomic_swap (machine_mode mode, rtx dst, rtx value, - rtx mem, rtx model) -{ - emit_insn (gen_aarch64_atomic_swp (mode, dst, mem, value, model)); -} - /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the location to store the data read from memory. OUT_RESULT is the location to store the result of the operation. MEM is the memory location to read and @@ -14450,10 +14441,6 @@ aarch64_gen_atomic_ldop (enum rtx_code code, rtx out_data, rtx out_result, a SET then emit a swap instruction and finish. */ switch (code) { - case SET: - aarch64_emit_atomic_swap (mode, out_data, src, mem, model_rtx); - return; - case MINUS: /* Negate the value and treat it as a PLUS. */ { diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index c00a18675b4..63384f9f99c 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -136,7 +136,7 @@ (define_expand "atomic_exchange" [(match_operand:ALLI 0 "register_operand" "") (match_operand:ALLI 1 "aarch64_sync_memory_operand" "") - (match_operand:ALLI 2 "register_operand" "") + (match_operand:ALLI 2 "aarch64_reg_or_zero" "") (match_operand:SI 3 "const_int_operand" "")] "" { @@ -156,10 +156,10 @@ (define_insn_and_split "aarch64_atomic_exchange" [(set (match_operand:ALLI 0 "register_operand" "=&r") ;; output - (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory + (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory (set (match_dup 1) (unspec_volatile:ALLI - [(match_operand:ALLI 2 "register_operand" "r") ;; input + [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ") ;; input (match_operand:SI 3 "const_int_operand" "")] ;; model UNSPECV_ATOMIC_EXCHG)) (clobber (reg:CC CC_REGNUM)) @@ -175,22 +175,25 @@ } ) -(define_insn_and_split "aarch64_atomic_exchange_lse" - [(set (match_operand:ALLI 0 "register_operand" "=&r") +(define_insn "aarch64_atomic_exchange_lse" + [(set (match_operand:ALLI 0 "register_operand" "=r") (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) (set (match_dup 1) (unspec_volatile:ALLI - [(match_operand:ALLI 2 "register_operand" "r") + [(match_operand:ALLI 2 "aarch64_reg_or_zero" "rZ") (match_operand:SI 3 "const_int_operand" "")] UNSPECV_ATOMIC_EXCHG))] "TARGET_LSE" - "#" - "&& reload_completed" - [(const_int 0)] { - aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1], - operands[2], operands[3]); - DONE; + enum memmodel model = memmodel_from_int (INTVAL (operands[3])); + if (is_mm_relaxed (model)) + return "swp\t%2, %0, %1"; + else if (is_mm_acquire (model) || is_mm_consume (model)) + return "swpa\t%2, %0, %1"; + else if (is_mm_release (model)) + return "swpl\t%2, %0, %1"; + else + return "swpal\t%2, %0, %1"; } ) @@ -585,28 +588,6 @@ ;; ARMv8.1-A LSE instructions. -;; Atomic swap with memory. -(define_insn "@aarch64_atomic_swp" - [(set (match_operand:ALLI 0 "register_operand" "+&r") - (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) - (set (match_dup 1) - (unspec_volatile:ALLI - [(match_operand:ALLI 2 "register_operand" "r") - (match_operand:SI 3 "const_int_operand" "")] - UNSPECV_ATOMIC_SWP))] - "TARGET_LSE && reload_completed" - { - enum memmodel model = memmodel_from_int (INTVAL (operands[3])); - if (is_mm_relaxed (model)) - return "swp\t%2, %0, %1"; - else if (is_mm_acquire (model) || is_mm_consume (model)) - return "swpa\t%2, %0, %1"; - else if (is_mm_release (model)) - return "swpl\t%2, %0, %1"; - else - return "swpal\t%2, %0, %1"; - }) - ;; Atomic load-op: Load data, operate, store result, keep data. (define_insn "@aarch64_atomic_load"