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[209.132.180.131]) by mx.google.com with ESMTPS id z3-v6si22883346plb.228.2018.05.25.01.43.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 May 2018 01:43:49 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-478479-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=AV/zbKeN; spf=pass (google.com: domain of gcc-patches-return-478479-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-478479-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; q=dns; s=default; b=tq7 YAFLubOVzOWhiRgygTjg7hiasuni8DCUIRqEO7+jb9kpglpt17IEMTNEs/CfTux/ ICb65qTQk6Nmh9dLEJHPh/u18NBs1a4InWga4gHiNnB2p2JCeeiVqcUoA3+88zsK 3az0yoJEoOqdWNaqrSJyxJCYSh3NOEVE5Lr4q6iY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references:mime-version :content-type:content-transfer-encoding; s=default; bh=ZJbCtrZZw ervOlkyJTUg8ylnKDw=; b=AV/zbKeNBc6aMbJTGcDzES8upGqplvdjAu7MT4dZ3 zdSjHKjoIVH9j23dOgTBUkIPK00bTuTVMS+4zNpVQ71Mpve2n2E6tIR007uaMWjW wurjrGFF1g6fNtnTiSYiUUCcHivPYu22IiX6QHWIfXP9laB+BB1azcUUv7j2AKnt XI= Received: (qmail 124489 invoked by alias); 25 May 2018 08:25:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73745 invoked by uid 89); 25 May 2018 08:08:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-27.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx07-00178001.pphosted.com Received: from mx08-00178001.pphosted.com (HELO mx07-00178001.pphosted.com) (91.207.212.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 May 2018 08:08:57 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w4P7xObS010120; Fri, 25 May 2018 10:08:55 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2j59j8k6kr-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 25 May 2018 10:08:55 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7D3A731; Fri, 25 May 2018 08:08:53 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 62B4C2424; Fri, 25 May 2018 08:08:53 +0000 (GMT) Received: from gnb.st.com (10.75.127.51) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 25 May 2018 10:08:52 +0200 From: Christophe Lyon To: , Subject: [ARM/FDPIC 14/21] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture Date: Fri, 25 May 2018 10:03:27 +0200 Message-ID: <20180525080354.13295-15-christophe.lyon@st.com> In-Reply-To: <20180525080354.13295-1-christophe.lyon@st.com> References: <20180525080354.13295-1-christophe.lyon@st.com> MIME-Version: 1.0 X-ClientProxiedBy: SFHDAG1NODE2.st.com (10.75.127.2) To SFHDAG5NODE1.st.com (10.75.127.13) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-05-25_03:, , signatures=0 X-IsSubscribed: yes Without this, when we are unwinding across a signal frame we can jump to an even address which leads to an exception. This is needed in __gnu_persnality_sigframe_fdpic() when restoring the PC from the signal frame since the PC saved by the kernel has the LSB bit set to zero. 2018-XX-XX Christophe Lyon Mickaël Guêné libgcc/ * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle v7m architecture. Change-Id: Ie84de548226bcf1751e19a09e8f091fb3013ccea -- 2.6.3 diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c index 564e4f13..6da6e3d 100644 --- a/libgcc/config/arm/unwind-arm.c +++ b/libgcc/config/arm/unwind-arm.c @@ -198,6 +198,11 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context, return _UVRSR_FAILED; vrs->core.r[regno] = *(_uw *) valuep; +#if defined(__ARM_ARCH_7M__) + /* Force LSB bit since we always run thumb code. */ + if (regno == 15) + vrs->core.r[regno] |= 1; +#endif return _UVRSR_OK; case _UVRSC_VFP: