From patchwork Thu Oct 6 17:51:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dr. David Alan Gilbert" X-Patchwork-Id: 4554 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3B38823DEE for ; Thu, 6 Oct 2011 17:51:32 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 2BA54A18DB5 for ; Thu, 6 Oct 2011 17:51:32 +0000 (UTC) Received: by bke5 with SMTP id 5so4882024bke.11 for ; Thu, 06 Oct 2011 10:51:32 -0700 (PDT) Received: by 10.223.92.152 with SMTP id r24mr4925729fam.19.1317923491748; Thu, 06 Oct 2011 10:51:31 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.23.170 with SMTP id n10cs138227laf; Thu, 6 Oct 2011 10:51:31 -0700 (PDT) Received: by 10.216.82.141 with SMTP id o13mr1496847wee.10.1317923490736; Thu, 06 Oct 2011 10:51:30 -0700 (PDT) Received: from mail-wy0-f178.google.com (mail-wy0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id v44si4683909wec.96.2011.10.06.10.51.30 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Oct 2011 10:51:30 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of david.gilbert@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of david.gilbert@linaro.org) smtp.mail=david.gilbert@linaro.org Received: by wyf23 with SMTP id 23so3643646wyf.37 for ; Thu, 06 Oct 2011 10:51:30 -0700 (PDT) Received: by 10.216.132.4 with SMTP id n4mr1545425wei.111.1317923489853; Thu, 06 Oct 2011 10:51:29 -0700 (PDT) Received: from davesworkthinkpad (gbibp9ph1--blueice2n1.emea.ibm.com. [195.212.29.75]) by mx.google.com with ESMTPS id h39sm11509727wbo.0.2011.10.06.10.51.28 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Oct 2011 10:51:29 -0700 (PDT) Date: Thu, 6 Oct 2011 18:51:25 +0100 From: "Dr. David Alan Gilbert" To: gcc-patches@gcc.gnu.org Cc: Ramana Radhakrishnan , rth@redhat.com, joseph@codesourcery.com, patches@linaro.org, mikestump@comcast.net, ro@CeBiTec.Uni-Bielefeld.DE Subject: [Patch 1/5] ARM 64 bit sync atomic operations [V3] Message-ID: <20111006175124.GB12770@davesworkthinkpad> References: <20110701155254.GA5242@davesworkthinkpad> <20110726085910.GA6925@davesworkthinkpad> <20110726090039.GB6925@davesworkthinkpad> <20111006174941.GA12770@davesworkthinkpad> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20111006174941.GA12770@davesworkthinkpad> User-Agent: Mutt/1.5.20 (2009-06-14) gcc/ * config/arm/arm.c (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1 diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 993e3a0..f6f1da7 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -288,7 +288,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HAVE_DMB (arm_arch7) /* Nonzero if this chip implements a memory barrier via CP15. */ -#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) +#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ + && ! TARGET_THUMB1) /* Nonzero if this chip implements a memory barrier instruction. */ #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)