From patchwork Fri Sep 23 16:03:21 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Weigand X-Patchwork-Id: 4305 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8A41723F6F for ; Fri, 23 Sep 2011 16:03:31 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 73456A18715 for ; Fri, 23 Sep 2011 16:03:31 +0000 (UTC) Received: by fxe23 with SMTP id 23so5515634fxe.11 for ; Fri, 23 Sep 2011 09:03:31 -0700 (PDT) Received: by 10.223.55.136 with SMTP id u8mr2407248fag.46.1316793811259; Fri, 23 Sep 2011 09:03:31 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.18.198 with SMTP id y6cs218550lad; Fri, 23 Sep 2011 09:03:30 -0700 (PDT) Received: by 10.227.174.72 with SMTP id s8mr2714519wbz.8.1316793804317; Fri, 23 Sep 2011 09:03:24 -0700 (PDT) Received: from mtagate3.uk.ibm.com (mtagate3.uk.ibm.com. [194.196.100.163]) by mx.google.com with ESMTPS id ev1si10501733wbb.90.2011.09.23.09.03.23 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 23 Sep 2011 09:03:24 -0700 (PDT) Received-SPF: pass (google.com: domain of uweigand@de.ibm.com designates 194.196.100.163 as permitted sender) client-ip=194.196.100.163; Authentication-Results: mx.google.com; spf=pass (google.com: domain of uweigand@de.ibm.com designates 194.196.100.163 as permitted sender) smtp.mail=uweigand@de.ibm.com Received: from d06nrmr1307.portsmouth.uk.ibm.com (d06nrmr1307.portsmouth.uk.ibm.com [9.149.38.129]) by mtagate3.uk.ibm.com (8.13.1/8.13.1) with ESMTP id p8NG3N9a029830; Fri, 23 Sep 2011 16:03:23 GMT Received: from d06av02.portsmouth.uk.ibm.com (d06av02.portsmouth.uk.ibm.com [9.149.37.228]) by d06nrmr1307.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p8NG3MNS2461696; Fri, 23 Sep 2011 17:03:23 +0100 Received: from d06av02.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p8NN3HGd018604; Fri, 23 Sep 2011 17:03:18 -0600 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with SMTP id p8NN3Gjt018587; Fri, 23 Sep 2011 17:03:16 -0600 Message-Id: <201109232303.p8NN3Gjt018587@d06av02.portsmouth.uk.ibm.com> Received: by tuxmaker.boeblingen.de.ibm.com (sSMTP sendmail emulation); Fri, 23 Sep 2011 18:03:21 +0200 Subject: Re: [patch, arm] Fix PR target/50305 (arm_legitimize_reload_address problem) To: michael.hope@linaro.org (Michael Hope) Date: Fri, 23 Sep 2011 18:03:21 +0200 (CEST) From: "Ulrich Weigand" Cc: gcc-patches@gcc.gnu.org, rearnsha@arm.com, ramana.radhakrishnan@linaro.org, patches@linaro.org In-Reply-To: from "Michael Hope" at Sep 12, 2011 09:50:45 AM X-Mailer: ELM [version 2.5 PL2] MIME-Version: 1.0 Michael Hope wrote: > On Sat, Sep 10, 2011 at 5:04 AM, Ulrich Weigand wrote: > > the problem in PR 50305 turned out to be caused by the ARM back-end > > LEGITIMIZE_RELOAD_ADDRESS implementation. > > Interesting the fault goes away with -mfpu=neon, perhaps due to the DI > mode operations getting pushed out into NEON registers. You might > want to be explicit about the FPU in dg-options. Hmm, reload problems tend to be very difficult to reproduce in general, everything need to line up just so ... For some reason, I didn't see the -mfpu=neon effect you describe; I'm seeing the reload failure with that setting as well. Nevertheless, I've updated the dg-options as suggested. I've also added a dg-skip-if line to prevent problems when using a -march multilib (as currently discussed in other threads ...). Richard/Ramana, any thoughts on this? Is this OK? Thanks, Ulrich ChangeLog: gcc/ PR target/50305 * config/arm/arm.c (arm_legitimize_reload_address): Recognize output of a previous pass through legitimize_reload_address. Do not attempt to optimize addresses if the base register is equivalent to a constant. gcc/testsuite/ PR target/50305 * gcc.target/arm/pr50305.c: New test. Index: gcc/testsuite/gcc.target/arm/pr50305.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr50305.c (revision 0) +++ gcc/testsuite/gcc.target/arm/pr50305.c (revision 0) @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */ +/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3" } */ + +struct event { + unsigned long long id; + unsigned int flag; +}; + +void dummy(void) +{ + /* This is here to ensure that the offset of perf_event_id below + relative to the LANCHOR symbol exceeds the allowed displacement. */ + static int __warned[300]; + __warned[0] = 1; +} + +extern void *kmem_cache_alloc_trace (void *cachep); +extern void *cs_cachep; +extern int nr_cpu_ids; + +struct event * +event_alloc (int cpu) +{ + static unsigned long long __attribute__((aligned(8))) perf_event_id; + struct event *event; + unsigned long long result; + unsigned long tmp; + + if (cpu >= nr_cpu_ids) + return 0; + + event = kmem_cache_alloc_trace (cs_cachep); + + __asm__ __volatile__ ("dmb" : : : "memory"); + + __asm__ __volatile__("@ atomic64_add_return\n" +"1: ldrexd %0, %H0, [%3]\n" +" adds %0, %0, %4\n" +" adc %H0, %H0, %H4\n" +" strexd %1, %0, %H0, [%3]\n" +" teq %1, #0\n" +" bne 1b" + : "=&r" (result), "=&r" (tmp), "+Qo" (perf_event_id) + : "r" (&perf_event_id), "r" (1LL) + : "cc"); + + __asm__ __volatile__ ("dmb" : : : "memory"); + + event->id = result; + + if (cpu) + event->flag = 1; + + for (cpu = 0; cpu < nr_cpu_ids; cpu++) + kmem_cache_alloc_trace (cs_cachep); + + return event; +} + Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 179082) +++ gcc/config/arm/arm.c (working copy) @@ -6550,9 +6550,26 @@ int opnum, int type, int ind_levels ATTRIBUTE_UNUSED) { + /* We must recognize output that we have already generated ourselves. */ if (GET_CODE (*p) == PLUS + && GET_CODE (XEXP (*p, 0)) == PLUS + && GET_CODE (XEXP (XEXP (*p, 0), 0)) == REG + && GET_CODE (XEXP (XEXP (*p, 0), 1)) == CONST_INT + && GET_CODE (XEXP (*p, 1)) == CONST_INT) + { + push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, + MODE_BASE_REG_CLASS (mode), GET_MODE (*p), + VOIDmode, 0, 0, opnum, (enum reload_type) type); + return true; + } + + if (GET_CODE (*p) == PLUS && GET_CODE (XEXP (*p, 0)) == REG && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0))) + /* If the base register is equivalent to a constant, let the generic + code handle it. Otherwise we will run into problems if a future + reload pass decides to rematerialize the constant. */ + && !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p, 0))) && GET_CODE (XEXP (*p, 1)) == CONST_INT) { HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));