From patchwork Tue Jul 26 09:02:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dr. David Alan Gilbert" X-Patchwork-Id: 3127 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4ABD623F41 for ; Tue, 26 Jul 2011 09:02:33 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id 1721EA18696 for ; Tue, 26 Jul 2011 09:02:33 +0000 (UTC) Received: by qwb8 with SMTP id 8so137379qwb.11 for ; Tue, 26 Jul 2011 02:02:32 -0700 (PDT) Received: by 10.229.68.200 with SMTP id w8mr436371qci.114.1311670952257; Tue, 26 Jul 2011 02:02:32 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.217.78 with SMTP id hl14cs103982qcb; Tue, 26 Jul 2011 02:02:32 -0700 (PDT) Received: by 10.227.55.69 with SMTP id t5mr4744025wbg.110.1311670951288; Tue, 26 Jul 2011 02:02:31 -0700 (PDT) Received: from anchor-post-2.mail.demon.net (anchor-post-2.mail.demon.net [195.173.77.133]) by mx.google.com with ESMTP id fd19si492936wbb.72.2011.07.26.02.02.30; Tue, 26 Jul 2011 02:02:31 -0700 (PDT) Received-SPF: neutral (google.com: 195.173.77.133 is neither permitted nor denied by best guess record for domain of david.gilbert@linaro.org) client-ip=195.173.77.133; Authentication-Results: mx.google.com; spf=neutral (google.com: 195.173.77.133 is neither permitted nor denied by best guess record for domain of david.gilbert@linaro.org) smtp.mail=david.gilbert@linaro.org Received: from tu006.demon.co.uk ([83.105.84.125] helo=gort.home.treblig.org) by anchor-post-2.mail.demon.net with esmtp (Exim 4.69) id 1QldX4-0002sZ-la; Tue, 26 Jul 2011 09:02:30 +0000 Received: from [192.168.66.106] (helo=davesworkthinkpad) by gort.home.treblig.org with esmtp (Exim 4.72) (envelope-from ) id 1QldX3-0001BJ-Bo; Tue, 26 Jul 2011 10:02:29 +0100 Date: Tue, 26 Jul 2011 10:02:29 +0100 From: "Dr. David Alan Gilbert" To: gcc-patches@gcc.gnu.org Cc: ramana.radhakrishnan@linaro.org, rth@redhat.com, joseph@codesourcery.com, patches@linaro.org Subject: [Patch 4/4] ARM 64 bit sync atomic operations [V2] Message-ID: <20110726090228.GE6925@davesworkthinkpad> References: <20110701155254.GA5242@davesworkthinkpad> <20110726085910.GA6925@davesworkthinkpad> <20110726090039.GB6925@davesworkthinkpad> <20110726090115.GC6925@davesworkthinkpad> <20110726090156.GD6925@davesworkthinkpad> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20110726090156.GD6925@davesworkthinkpad> User-Agent: Mutt/1.5.20 (2009-06-14) gcc/ * config/arm/arm.c (TARGET_HAVE_DMB_MCR) MCR Not available in Thumb1 but is available on armv6 diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 0d419d5..146b9ad 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -285,7 +285,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HAVE_DMB (arm_arch7) /* Nonzero if this chip implements a memory barrier via CP15. */ -#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) +#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ + && ! TARGET_THUMB1) /* Nonzero if this chip implements a memory barrier instruction. */ #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)