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[209.132.180.131]) by mx.google.com with ESMTPS id l26si1751315pli.44.2016.12.01.13.43.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Dec 2016 13:43:26 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-443260-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-443260-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-443260-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=nJFxYBqDLpLXEypf IbP6SniJlr3YsqDCEgUdtlnNSchbxhstVBgxahvlFuSgUCOmtlS25gBPz0z1YB0U rzzNHSVikFAJ1rmB4G9pm/lLRo7/nSAAXy7XYCsKL+KjmY1jSLS6bGm2Uuy8L9LH oCd5xLCqKEo4ZdgICc3dJtkzLQI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=/GZsZfRX7JZNQDm25vRMqp r65VU=; b=idjHis0hiOmidw1HmCe0q9mvsi4jUhmrr7cvNNN4RPwGqbxkLgfE9p pCDypmPPhFjCSNvYSPjAQFv/WiQIsoDqNNt9wnW1hBHCeD/kK/k8g7SbD4FzjIn1 GJq4i7rziHJIzuYVhdgsLQNsbj7pr1hVodxIiIiJ+jJG2zsIxjht8= Received: (qmail 43663 invoked by alias); 1 Dec 2016 21:43:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 43618 invoked by uid 89); 1 Dec 2016 21:43:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=no version=3.3.2 spammy=sk:text_se, Compile, 8367, Modes X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Dec 2016 21:43:00 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id CF2DC812E0 for ; Thu, 1 Dec 2016 22:42:57 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JKCRj8Hd6AHM for ; Thu, 1 Dec 2016 22:42:57 +0100 (CET) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 97DE98134D for ; Thu, 1 Dec 2016 22:42:57 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Preparatory work for switch to LRA Date: Thu, 01 Dec 2016 22:42:56 +0100 Message-ID: <1817665.dyyKgqe4Hx@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-48-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 The switch will very likely not happen for GCC 7, but an experimental support can probably be introduced. The attached patch adds the famous -mlra option and rescues straightforward changes by DaveM. Tested on SPARC/Solaris, applied on the mainline. 2016-12-01 Eric Botcazou David S. Miller * config/sparc/sparc.opt (mlra): New target option. * config/sparc/sparc.c (TARGET_LRA_P): Define to... (sparc_lra_p): ...this. New function. (D_MODES, DF_MODES): Add missing cast. * config/sparc/sparc.md (*movsi_lo_sum, *movsi_high): Do not provide these insns when flag_pic. (sethi_di_medlow, losum_di_medlow, seth44, setm44, setl44, sethh, setlm, sethm, setlo, embmedany_sethi, embmedany_losum, embmedany_brsum, embmedany_textuhi, embmedany_texthi, embmedany_textulo, embmedany_textlo): Likewise. (sethi_di_medlow_embmedany_pic): Provide it only when flag_pic. -- Eric Botcazou Index: config/sparc/sparc.c =================================================================== --- config/sparc/sparc.c (revision 243096) +++ config/sparc/sparc.c (working copy) @@ -639,6 +639,7 @@ static const char *sparc_mangle_type (co static void sparc_trampoline_init (rtx, tree, rtx); static machine_mode sparc_preferred_simd_mode (machine_mode); static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass); +static bool sparc_lra_p (void); static bool sparc_print_operand_punct_valid_p (unsigned char); static void sparc_print_operand (FILE *, rtx, int); static void sparc_print_operand_address (FILE *, machine_mode, rtx); @@ -836,7 +837,7 @@ char sparc_hard_reg_printed[8]; #endif #undef TARGET_LRA_P -#define TARGET_LRA_P hook_bool_void_false +#define TARGET_LRA_P sparc_lra_p #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p @@ -4787,7 +4788,7 @@ enum sparc_mode_class { ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE)) /* Modes for double-word and smaller quantities. */ -#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) +#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) /* Modes for quad-word and smaller quantities. */ #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) @@ -4799,7 +4800,7 @@ enum sparc_mode_class { #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) /* Modes for double-float and smaller quantities. */ -#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) +#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) /* Modes for quad-float and smaller quantities. */ #define TF_MODES (DF_MODES | (1 << (int) TF_MODE)) @@ -12248,6 +12249,14 @@ sparc_preferred_reload_class (rtx x, reg return rclass; } +/* Return true if we use LRA instead of reload pass. */ + +static bool +sparc_lra_p (void) +{ + return TARGET_LRA; +} + /* Output a wide multiply instruction in V8+ mode. INSN is the instruction, OPERANDS are its operands and OPCODE is the mnemonic to be used. */ Index: config/sparc/sparc.md =================================================================== --- config/sparc/sparc.md (revision 243096) +++ config/sparc/sparc.md (working copy) @@ -1568,13 +1568,13 @@ (define_insn "*movsi_lo_sum" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")))] - "" + "!flag_pic" "or\t%1, %%lo(%a2), %0") (define_insn "*movsi_high" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (match_operand:SI 1 "immediate_operand" "in")))] - "" + "!flag_pic" "sethi\t%%hi(%a1), %0") ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC @@ -1846,27 +1846,27 @@ (define_insn "movdi_pic_gotdata_op" (define_insn "*sethi_di_medlow_embmedany_pic" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "medium_pic_operand" "")))] - "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)" + "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && flag_pic && check_pic (1)" "sethi\t%%hi(%a1), %0") (define_insn "*sethi_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "symbolic_operand" "")))] - "TARGET_CM_MEDLOW && check_pic (1)" + "TARGET_CM_MEDLOW && !flag_pic" "sethi\t%%hi(%a1), %0") (define_insn "*losum_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] - "TARGET_CM_MEDLOW" + "TARGET_CM_MEDLOW && !flag_pic" "or\t%1, %%lo(%a2), %0") (define_insn "seth44" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))] - "TARGET_CM_MEDMID" + "TARGET_CM_MEDMID && !flag_pic" "sethi\t%%h44(%a1), %0") (define_insn "setm44" @@ -1874,28 +1874,28 @@ (define_insn "setm44" (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))] - "TARGET_CM_MEDMID" + "TARGET_CM_MEDMID && !flag_pic" "or\t%1, %%m44(%a2), %0") (define_insn "setl44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] - "TARGET_CM_MEDMID" + "TARGET_CM_MEDMID && !flag_pic" "or\t%1, %%l44(%a2), %0") (define_insn "sethh" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))] - "TARGET_CM_MEDANY" + "TARGET_CM_MEDANY && !flag_pic" "sethi\t%%hh(%a1), %0") (define_insn "setlm" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))] - "TARGET_CM_MEDANY" + "TARGET_CM_MEDANY && !flag_pic" "sethi\t%%lm(%a1), %0") (define_insn "sethm" @@ -1903,49 +1903,49 @@ (define_insn "sethm" (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))] - "TARGET_CM_MEDANY" + "TARGET_CM_MEDANY && !flag_pic" "or\t%1, %%hm(%a2), %0") (define_insn "setlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] - "TARGET_CM_MEDANY" + "TARGET_CM_MEDANY && !flag_pic" "or\t%1, %%lo(%a2), %0") (define_insn "embmedany_sethi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))] - "TARGET_CM_EMBMEDANY && check_pic (1)" + "TARGET_CM_EMBMEDANY && !flag_pic" "sethi\t%%hi(%a1), %0") (define_insn "embmedany_losum" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "data_segment_operand" "")))] - "TARGET_CM_EMBMEDANY" + "TARGET_CM_EMBMEDANY && !flag_pic" "add\t%1, %%lo(%a2), %0") (define_insn "embmedany_brsum" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))] - "TARGET_CM_EMBMEDANY" + "TARGET_CM_EMBMEDANY && !flag_pic" "add\t%1, %_, %0") (define_insn "embmedany_textuhi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))] - "TARGET_CM_EMBMEDANY && check_pic (1)" + "TARGET_CM_EMBMEDANY && !flag_pic" "sethi\t%%uhi(%a1), %0") (define_insn "embmedany_texthi" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))] - "TARGET_CM_EMBMEDANY && check_pic (1)" + "TARGET_CM_EMBMEDANY && !flag_pic" "sethi\t%%hi(%a1), %0") (define_insn "embmedany_textulo" @@ -1953,14 +1953,14 @@ (define_insn "embmedany_textulo" (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))] - "TARGET_CM_EMBMEDANY" + "TARGET_CM_EMBMEDANY && !flag_pic" "or\t%1, %%ulo(%a2), %0") (define_insn "embmedany_textlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "text_segment_operand" "")))] - "TARGET_CM_EMBMEDANY" + "TARGET_CM_EMBMEDANY && !flag_pic" "or\t%1, %%lo(%a2), %0") ;; Now some patterns to help reload out a bit. @@ -1968,9 +1968,7 @@ (define_expand "reload_indi" [(parallel [(match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "immediate_operand" "") (match_operand:TI 2 "register_operand" "=&r")])] - "(TARGET_CM_MEDANY - || TARGET_CM_EMBMEDANY) - && !flag_pic" + "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && !flag_pic" { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; @@ -1980,9 +1978,7 @@ (define_expand "reload_outdi" [(parallel [(match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "immediate_operand" "") (match_operand:TI 2 "register_operand" "=&r")])] - "(TARGET_CM_MEDANY - || TARGET_CM_EMBMEDANY) - && !flag_pic" + "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && !flag_pic" { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; Index: config/sparc/sparc.opt =================================================================== --- config/sparc/sparc.opt (revision 243096) +++ config/sparc/sparc.opt (working copy) @@ -57,6 +57,10 @@ msoft-quad-float Target Report RejectNegative InverseMask(HARD_QUAD) Do not use hardware quad fp instructions. +mlra +Target Report Mask(LRA) +Enable Local Register Allocation. + mv8plus Target Report Mask(V8PLUS) Compile for V8+ ABI.