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Tue, 26 Jan 2016 16:04:51 +0000 From: James Greenhalgh To: CC: , , Subject: [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS Date: Tue, 26 Jan 2016 16:04:47 +0000 Message-ID: <1453824287-37678-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; DB3FFO11FD020; 1:38b6xYmXgZEmfmc8QoyDmjsibbK9PK2XbN2KmclSlUqIA9JkXofQNMxJadlJPKdtwpqgwidHppLtTA1vm9g8Og+ljBwBZTDVq5RePFc9K0FySpVC042Q4qPgALUR6Pqciosq/EO7ej6nL9oxYpwtFqNMi/pKeoW2KYb35kk8G7rECEXeyH9iuZyBMRVfXIEVPAsOAsNXSnWSpsUDcyfX2rQHedO69gwtEtJg6cpe0y7dZCUT/tFMpAtkHdu7XCazsvkXj46U0ok7wx73736sckGt1c+oaGenfLXRHfl0TqjNYjvjIq8gBwiX0ApVkYdnlAjhisNRtckzVT3J4hIZ6GLoZnyyFx/XkASLxnGEMbEZ/iFtsHno1Inc3wwGLcnPewDEj28PBeo5arCe75DThprza5+mG1J/AoPERj2n5Fo= X-Forefront-Antispam-Report: CIP:217.140.96.140; CTRY:GB; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(164054003)(377424004)(11100500001)(4610100001)(229853001)(5000100001)(50986999)(86362001)(87936001)(36756003)(26826002)(50226001)(92566002)(2906002)(4326007)(6806005)(104016004)(2351001)(19580395003)(5890100001)(5008740100001)(77096005)(106466001)(450100001)(84326002)(5003600100002)(1096002)(512874002)(110136002)(2476003)(189998001)(1220700001)(586003)(568964002)(33646002)(19580405001); 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DB3PR08MB0106; 5:fr18TN3FhocRcWjY6poWOMwOvcQzUqaakXGMn6w9SypF2amwhxEI2rxWVFOzh/34UTtXZoiinh65qgE57ve9vynzyI67pox1ws/TINTPmgVWbQBRRZC9vB7yeSbBXC5+DG8797zZIYg5+a7LHd0Wuw==; 24:OPD8Zeuj6ODtEthKXAb76xpZL/W/ZvwOkr+fm/5GSHvC6k5QGsW3V6nu82Jfrw8rcLoMOMyCB4ddhkeLpFREFBcyyNJ/z7bOxv0ayrEih7k=; 20:P72krtjeN15y/Cltr3kGk/IeQkhdfJmQWo7V7HA5xzrgpo30QMYERam4DYfNepCi9ZfQto3rximDsCLavRh24QJuMkIpzEDSR3uuY7ezGWfi1DlR9Kzk/LAPJ4X2uz3qlhBb6PbufsxtYwywMbfpYf64LIXe4KPcSCMpI6QAorI= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2016 16:04:53.0697 (UTC) X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[217.140.96.140]; Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR08MB0106 X-MC-Unique: 4vkLY7MgRtar5tQtPLvIXA-1 X-IsSubscribed: yes Hi, In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction available when compiling with -march=armv8.1-a are only usable with a register number in the range 0 to 15 for operand 3, as gas will point out: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]' This patch teaches GCC to avoid registers outside of this range when appropriate, in the same fashion as we do for other instructions with this limitation. Tested on an internal testsuite targeting Neon intrinsics. OK? Thanks, James --- 2016-01-25 James Greenhalgh * config/aarch64/aarch64.md (arch64_sqrdmlh_lane): Fix register constraints for operand 3. (aarch64_sqrdmlh_laneq): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index e1f5682..0b46e78 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3240,7 +3240,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select: - (match_operand: 3 "register_operand" "w") + (match_operand: 3 "register_operand" "") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3258,7 +3258,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select: - (match_operand: 3 "register_operand" "w") + (match_operand: 3 "register_operand" "") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3278,7 +3278,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select: - (match_operand: 3 "register_operand" "w") + (match_operand: 3 "register_operand" "") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3296,7 +3296,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select: - (match_operand: 3 "register_operand" "w") + (match_operand: 3 "register_operand" "") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA"