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[209.132.180.131]) by mx.google.com with ESMTPS id 67si3204668ioe.85.2015.09.25.08.05.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Sep 2015 08:05:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-408352-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 13702 invoked by alias); 25 Sep 2015 15:05:17 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13514 invoked by uid 89); 25 Sep 2015 15:05:16 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=unavailable version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Sep 2015 15:05:04 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-26-qlqs4g-ISeqLKX6NrZRajQ-1; Fri, 25 Sep 2015 16:04:58 +0100 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 25 Sep 2015 16:04:58 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: ramana.radhakrishnan@arm.com, bernds_cb1@t-online.de, law@redhat.com, ebotcazou@libertysurf.fr, steven@gcc.gnu.org Subject: [Patch ifcvt 2/3] Move noce_if_info in to ifcvt.h Date: Fri, 25 Sep 2015 16:04:37 +0100 Message-Id: <1443193479-10830-3-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <1443193479-10830-1-git-send-email-james.greenhalgh@arm.com> References: <20150911095608.GA2448@arm.com> <1443193479-10830-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: qlqs4g-ISeqLKX6NrZRajQ-1 X-IsSubscribed: yes X-Original-Sender: james.greenhalgh@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::235 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Simple code move. We're going to allow targets to work with this information, so pull it somewhere they can see it. No issues building toolchains after this transformation. OK? Thanks, James --- 2015-09-26 James Greenhalgh * ifcvt.c (noce_if_info): Move to... * ifcvt.h (noce_if_info): ...Here. diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index e89d567..d7fc523 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -769,67 +769,6 @@ cond_exec_process_if_block (ce_if_block * ce_info, return FALSE; } -/* Used by noce_process_if_block to communicate with its subroutines. - - The subroutines know that A and B may be evaluated freely. They - know that X is a register. They should insert new instructions - before cond_earliest. */ - -struct noce_if_info -{ - /* The basic blocks that make up the IF-THEN-{ELSE-,}JOIN block. */ - basic_block test_bb, then_bb, else_bb, join_bb; - - /* The jump that ends TEST_BB. */ - rtx_insn *jump; - - /* The jump condition. */ - rtx cond; - - /* New insns should be inserted before this one. */ - rtx_insn *cond_earliest; - - /* Insns in the THEN and ELSE block. There is always just this - one insns in those blocks. The insns are single_set insns. - If there was no ELSE block, INSN_B is the last insn before - COND_EARLIEST, or NULL_RTX. In the former case, the insn - operands are still valid, as if INSN_B was moved down below - the jump. */ - rtx_insn *insn_a, *insn_b; - - /* The SET_SRC of INSN_A and INSN_B. */ - rtx a, b; - - /* The SET_DEST of INSN_A. */ - rtx x; - - /* True if this if block is not canonical. In the canonical form of - if blocks, the THEN_BB is the block reached via the fallthru edge - from TEST_BB. For the noce transformations, we allow the symmetric - form as well. */ - bool then_else_reversed; - - /* True if the contents of then_bb and else_bb are a - simple single set instruction. */ - bool then_simple; - bool else_simple; - - /* The total rtx cost of the instructions in then_bb and else_bb. */ - unsigned int then_cost; - unsigned int else_cost; - - /* Estimated cost of the particular branch instruction. */ - unsigned int branch_cost; - - /* For if-convert transformations, the legacy way to decide whether - the transformation should be applied is a comparison of a magic - number against BRANCH_COST. Ultimately, this should go away, but - to avoid regressing targets this field encodes that number so the - profitability analysis can remain unchanged. */ - unsigned int magic_number; - -}; - static rtx noce_emit_store_flag (struct noce_if_info *, rtx, int, int); static int noce_try_move (struct noce_if_info *); static int noce_try_store_flag (struct noce_if_info *); diff --git a/gcc/ifcvt.h b/gcc/ifcvt.h index 3e3dc5b..f1c2dc9 100644 --- a/gcc/ifcvt.h +++ b/gcc/ifcvt.h @@ -40,4 +40,64 @@ struct ce_if_block int pass; /* Pass number. */ }; +/* Used by noce_process_if_block to communicate with its subroutines. + + The subroutines know that A and B may be evaluated freely. They + know that X is a register. They should insert new instructions + before cond_earliest. */ + +struct noce_if_info +{ + /* The basic blocks that make up the IF-THEN-{ELSE-,}JOIN block. */ + basic_block test_bb, then_bb, else_bb, join_bb; + + /* The jump that ends TEST_BB. */ + rtx_insn *jump; + + /* The jump condition. */ + rtx cond; + + /* New insns should be inserted before this one. */ + rtx_insn *cond_earliest; + + /* Insns in the THEN and ELSE block. There is always just this + one insns in those blocks. The insns are single_set insns. + If there was no ELSE block, INSN_B is the last insn before + COND_EARLIEST, or NULL_RTX. In the former case, the insn + operands are still valid, as if INSN_B was moved down below + the jump. */ + rtx_insn *insn_a, *insn_b; + + /* The SET_SRC of INSN_A and INSN_B. */ + rtx a, b; + + /* The SET_DEST of INSN_A. */ + rtx x; + + /* True if this if block is not canonical. In the canonical form of + if blocks, the THEN_BB is the block reached via the fallthru edge + from TEST_BB. For the noce transformations, we allow the symmetric + form as well. */ + bool then_else_reversed; + + /* True if the contents of then_bb and else_bb are a + simple single set instruction. */ + bool then_simple; + bool else_simple; + + /* The total rtx cost of the instructions in then_bb and else_bb. */ + unsigned int then_cost; + unsigned int else_cost; + + /* Estimated cost of the particular branch instruction. */ + unsigned int branch_cost; + + /* For some if-convert transformations, the canonical way to decide + whether the transformation should be applied is a comparison of + a magic number against BRANCH_COST. Ultimately, this should go + away, but to avoid regressing targets this field encodes that + number so the profitability analysis can remain unchanged. */ + unsigned int magic_number; +}; + #endif /* GCC_IFCVT_H */