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[209.132.180.131]) by mx.google.com with ESMTPS id x75si2863327ioi.11.2015.09.25.06.20.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Sep 2015 06:20:14 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-408328-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 114892 invoked by alias); 25 Sep 2015 13:20:02 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 114863 invoked by uid 89); 25 Sep 2015 13:20:01 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Sep 2015 13:19:59 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-17-oHTvbbHmSGixHOWGSP1Zpw-1; Fri, 25 Sep 2015 14:19:52 +0100 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 25 Sep 2015 14:19:52 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: kyrtka01@arm.com, ramana.radhakrishnan@arm.com, marcus.shawcroft@arm.com, richard.earnshaw@arm.com Subject: Re: [Patch 1/2 AArch64/ARM] Give AArch64 ROR (Immediate) a new type attribute Date: Fri, 25 Sep 2015 14:19:47 +0100 Message-Id: <1443187187-19891-1-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <560543CF.2000909@arm.com> References: <560543CF.2000909@arm.com> MIME-Version: 1.0 X-MC-Unique: oHTvbbHmSGixHOWGSP1Zpw-1 X-IsSubscribed: yes X-Original-Sender: james.greenhalgh@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22a as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On Fri, Sep 25, 2015 at 01:53:35PM +0100, Kyrill Tkachov wrote: > Hi James, > > On 25/09/15 08:59, James Greenhalgh wrote: > > Hi, > > > > This patch splits the "shift_imm" type attribute used by AArch64 in > > two - giving rotate_imm and shift_imm. > > > > We then apply this transform across the AArch64 pipeline descriptions > > which have modelling for shift_imm (cortex-a53, cortex-a57, thunderx). > > This should give no functional change to these models. > > > > Bootstrapped and tested on aarch64-none-linux-gnu, and > > arm-none-linux-gnueabihf with no issues. > > > > OK? > > > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -3807,13 +3807,15 @@ > > ;; Rotate right > (define_insn "*ror3_insn" > - [(set (match_operand:GPI 0 "register_operand" "=r") > - (rotatert:GPI > - (match_operand:GPI 1 "register_operand" "r") > - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs")))] > + [(set (match_operand:GPI 0 "register_operand" "=r,r") > + (rotatert:GPI > + (match_operand:GPI 1 "register_operand" "r,r") > + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "r,Us")))] > "" > - "ror\\t%0, %1, %2" > - [(set_attr "type" "shift_reg")] > + "@ > + ror\\t%0, %1, %2 > + ror\\t%0, %1, %2" > + [(set_attr "type" "shift_reg, rotate_imm")] > ) > > AFAIK since the output template for the two alternatives is identical you > don't need to specify multiple identical output templates using '@'. You can > just specify the alternative values for the "type" attribute. > See the *sub_shiftsi pattern in the arm backend for an example of that. > > arm-wise this patch is ok since you don't actually introduce usage of the new > type to any arm patterns. Thanks for the review and the tip. Patch updated and attached after checking that the compiler still builds, and that we still schedule appropriately. Thanks, James --- 2015-09-25 James Greenhalgh * config/arm/types.md (type): Add rotate_imm. * config/aarch64/aarch64.md (*ror3_insn): Split out the ROR immediate case. (*rorsi3_insn_uxtw): Likewise. * config/aarch64/thunderx.md (thunderx_shift): Add rotate_imm. * config/arm/cortex-a53.md (cortex_a53_alu_shift): Add rotate_imm. * config/arm/cortex-a57.md (cortex_a53_alu): Add rotate_imm. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 78b9ae2..090ad65 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3807,13 +3807,13 @@ ;; Rotate right (define_insn "*ror3_insn" - [(set (match_operand:GPI 0 "register_operand" "=r") - (rotatert:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs")))] + [(set (match_operand:GPI 0 "register_operand" "=r,r") + (rotatert:GPI + (match_operand:GPI 1 "register_operand" "r,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "r,Us")))] "" "ror\\t%0, %1, %2" - [(set_attr "type" "shift_reg")] + [(set_attr "type" "shift_reg, rotate_imm")] ) ;; zero_extend version of above @@ -3902,7 +3902,7 @@ operands[3] = GEN_INT ( - UINTVAL (operands[2])); return "ror\\t%0, %1, %3"; } - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) ;; zero_extend version of the above @@ -3916,7 +3916,7 @@ operands[3] = GEN_INT (32 - UINTVAL (operands[2])); return "ror\\t%w0, %w1, %3"; } - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) (define_insn "*_ashl" diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index cf96368..3dae963 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -39,7 +39,7 @@ (define_insn_reservation "thunderx_shift" 1 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "bfm,extend,shift_imm,shift_reg,rbit,rev")) + (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev")) "thunderx_pipe0 | thunderx_pipe1") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index db572f6..3fa0625 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -76,7 +76,7 @@ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,csel,clz,rbit,rev,alu_dsp_reg,\ - shift_imm,shift_reg,\ + rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mrs,multiple,no_insn")) "cortex_a53_slot_any") diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index a32c848..d6ce440 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -296,7 +296,7 @@ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\ - shift_imm,shift_reg,\ + rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ mrs,multiple,no_insn")) diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index ec609ae..534be74 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -120,6 +120,7 @@ ; final output, thus having no impact on scheduling. ; rbit reverse bits. ; rev reverse bytes. +; rotate_imm rotate by immediate. ; sdiv signed division. ; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an ; immediate. @@ -627,6 +628,7 @@ nop,\ rbit,\ rev,\ + rotate_imm,\ sdiv,\ shift_imm,\ shift_reg,\