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[209.132.180.131]) by mx.google.com with ESMTPS id dh1si6045073pbc.144.2015.09.09.01.31.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Sep 2015 01:31:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-406948-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 117500 invoked by alias); 9 Sep 2015 08:31:41 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 117481 invoked by uid 89); 9 Sep 2015 08:31:40 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL, BAYES_05, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 09 Sep 2015 08:31:38 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-28-AyMjVF86Qd2Ffkb-U_T6sw-1; Wed, 09 Sep 2015 09:31:33 +0100 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 9 Sep 2015 09:31:32 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: christophe.lyon@linaro.org, marcus.shawcroft@arm.com, tejas.belagod@arm.com, alan.lawrence@arm.com Subject: [AArch64] Fix vcvt_high_f64_f32 and vcvt_figh_f32_f64 intrinsics. Date: Wed, 9 Sep 2015 09:31:28 +0100 Message-Id: <1441787488-19661-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: AyMjVF86Qd2Ffkb-U_T6sw-1 X-IsSubscribed: yes X-Original-Sender: james.greenhalgh@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22a as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, This patch clears up some remaining confusion in the vector lane orderings for the two intrinsics mentioned in the title. Bootstrapped on aarch64-none-linux-gnu and regression tested for aarch64_be-none-elf with no issues. OK? Thanks, James --- 2015-09-09 James Greenhalgh * config/aarch64/aarch64-simd.md (vec_unpacks_lo_v4sf): Rewrite as an expand. (vec_unpacks_hi_v4sf): Likewise. (aarch64_float_extend_lo_v2df): Rename to... (aarch64_fcvtl_v4sf): This. (aarch64_fcvtl2_v4sf): New. (aarch64_float_truncate_hi_v4sf): Rewrite as an expand. (aarch64_float_truncate_hi_v4sf_le): New. (aarch64_float_truncate_hi_v4sf_be): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 75fa0ab..c7ae956 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1691,39 +1691,65 @@ ;; Float widening operations. -(define_insn "vec_unpacks_lo_v4sf" +(define_insn "aarch64_float_extend_lo_v2df" [(set (match_operand:V2DF 0 "register_operand" "=w") (float_extend:V2DF - (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "w") - (parallel [(const_int 0) (const_int 1)]) - )))] + (match_operand:V2SF 1 "register_operand" "w")))] "TARGET_SIMD" "fcvtl\\t%0.2d, %1.2s" [(set_attr "type" "neon_fp_cvt_widen_s")] ) -(define_insn "aarch64_float_extend_lo_v2df" +(define_insn "aarch64_fcvtl_v4sf" [(set (match_operand:V2DF 0 "register_operand" "=w") (float_extend:V2DF - (match_operand:V2SF 1 "register_operand" "w")))] + (vec_select:V2SF + (match_operand:V4SF 1 "register_operand" "w") + (match_operand:V4SF 2 "vect_par_cnst_lo_half" ""))))] "TARGET_SIMD" "fcvtl\\t%0.2d, %1.2s" [(set_attr "type" "neon_fp_cvt_widen_s")] ) -(define_insn "vec_unpacks_hi_v4sf" +(define_insn "aarch64_fcvtl2_v4sf" [(set (match_operand:V2DF 0 "register_operand" "=w") (float_extend:V2DF (vec_select:V2SF (match_operand:V4SF 1 "register_operand" "w") - (parallel [(const_int 2) (const_int 3)]) - )))] + (match_operand:V4SF 2 "vect_par_cnst_hi_half" ""))))] "TARGET_SIMD" "fcvtl2\\t%0.2d, %1.4s" [(set_attr "type" "neon_fp_cvt_widen_s")] ) +(define_expand "vec_unpacks_lo_v4sf" + [(match_operand:V2DF 0 "register_operand" "=w") + (match_operand:V4SF 1 "register_operand" "w")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, false); + rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN + ? gen_aarch64_fcvtl2_v4sf + : gen_aarch64_fcvtl_v4sf; + emit_insn (gen (operands[0], operands[1], p)); + DONE; +} +) + +(define_expand "vec_unpacks_hi_v4sf" + [(match_operand:V2DF 0 "register_operand" "=w") + (match_operand:V4SF 1 "register_operand" "w")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, true); + rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN + ? gen_aarch64_fcvtl_v4sf + : gen_aarch64_fcvtl2_v4sf; + emit_insn (gen (operands[0], operands[1], p)); + DONE; +} +) + ;; Float narrowing operations. (define_insn "aarch64_float_truncate_lo_v2sf" @@ -1735,17 +1761,42 @@ [(set_attr "type" "neon_fp_cvt_narrow_d_q")] ) -(define_insn "aarch64_float_truncate_hi_v4sf" +(define_insn "aarch64_float_truncate_hi_v4sf_le" [(set (match_operand:V4SF 0 "register_operand" "=w") (vec_concat:V4SF (match_operand:V2SF 1 "register_operand" "0") (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "w"))))] - "TARGET_SIMD" + "TARGET_SIMD && !BYTES_BIG_ENDIAN" "fcvtn2\\t%0.4s, %2.2d" [(set_attr "type" "neon_fp_cvt_narrow_d_q")] ) +(define_insn "aarch64_float_truncate_hi_v4sf_be" + [(set (match_operand:V4SF 0 "register_operand" "=w") + (vec_concat:V4SF + (float_truncate:V2SF + (match_operand:V2DF 2 "register_operand" "w")) + (match_operand:V2SF 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "fcvtn2\\t%0.4s, %2.2d" + [(set_attr "type" "neon_fp_cvt_narrow_d_q")] +) + +(define_expand "aarch64_float_truncate_hi_v4sf" + [(match_operand:V4SF 0 "register_operand" "=w") + (match_operand:V2SF 1 "register_operand" "0") + (match_operand:V2DF 2 "register_operand" "w")] + "TARGET_SIMD" +{ + rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN + ? gen_aarch64_float_truncate_hi_v4sf_be + : gen_aarch64_float_truncate_hi_v4sf_le; + emit_insn (gen (operands[0], operands[1], operands[2])); + DONE; +} +) + (define_expand "vec_pack_trunc_v2df" [(set (match_operand:V4SF 0 "register_operand") (vec_concat:V4SF