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[90.80.39.29]) by smtp.gmail.com with ESMTPSA id ym2sm11587439wjc.44.2015.07.16.00.58.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Jul 2015 00:58:06 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [ARM] Fix vget_lane for big-endian targets Date: Thu, 16 Jul 2015 09:56:44 +0200 Message-Id: <1437033404-4759-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22f as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 AdvSIMD vget_lane tests currently fail on armeb targets when dealing with vectors of 2 64-bits elements. This patches fixes it, by adding a code fragment similar to what is dones in other cases. I could have simplified it a bit given that the vector width is known, but I chose to hardcode 'reg_nelts = 2' to keep the code closer to what is done elsewhere. OK for trunk? Christophe 2015-07-16 Christophe Lyon * config/arm/neon.md (neon_vget_lanev2di): Handle big-endian targets. diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 654d9d5..59ddc5b 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2736,6 +2736,19 @@ (match_operand:SI 2 "immediate_operand" "")] "TARGET_NEON" { + if (BYTES_BIG_ENDIAN) + { + /* The intrinsics are defined in terms of a model where the + element ordering in memory is vldm order, whereas the generic + RTL is defined in terms of a model where the element ordering + in memory is array order. Convert the lane number to conform + to this model. */ + unsigned int elt = INTVAL (operands[2]); + unsigned int reg_nelts = 2; + elt ^= reg_nelts - 1; + operands[2] = GEN_INT (elt); + } + switch (INTVAL (operands[2])) { case 0: