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[82.225.222.175]) by mx.google.com with ESMTPSA id jr4sm26100313wjc.20.2015.01.13.07.18.56 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Jan 2015 07:18:57 -0800 (PST) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests. Date: Tue, 13 Jan 2015 16:18:07 +0100 Message-Id: <1421162314-25779-10-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22d as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 * gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from vXXXhn.inc. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc new file mode 100644 index 0000000..0dbcc92 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc @@ -0,0 +1,50 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */ +#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \ + VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \ + VECT_VAR(vector2, T1, W, N)); \ + vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N)) + +#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \ + TEST_VADDHN1(INSN, T1, T2, W, W2, N) + + DECL_VARIABLE_64BITS_VARIANTS(vector64); + DECL_VARIABLE_128BITS_VARIANTS(vector1); + DECL_VARIABLE_128BITS_VARIANTS(vector2); + + clean_results (); + + /* Fill input vector1 and vector2 with arbitrary values */ + VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1)); + VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1)); + VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1)); + VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1)); + VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1)); + VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1)); + + VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX); + VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX); + VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX); + VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX); + VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX); + VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX); + + TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8); + TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4); + TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2); + TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8); + TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4); + TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2); + + CHECK_RESULTS (TEST_MSG, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c index 58fd5ea..88c92f3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c @@ -8,6 +8,9 @@ #include #endif +#define INSN_NAME vaddhn +#define TEST_MSG "VADDHN" + /* Expected results. */ VECT_VAR_DECL(expected,int,8,8) [] = { 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32 }; @@ -52,56 +55,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, 0x33333333, 0x33333333 }; -#define INSN_NAME vaddhn -#define TEST_MSG "VADDHN" - -#define FNNAME1(NAME) exec_ ## NAME -#define FNNAME(NAME) FNNAME1(NAME) - -void FNNAME (INSN_NAME) (void) -{ - /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */ -#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \ - VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \ - VECT_VAR(vector2, T1, W, N)); \ - vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N)) - -#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \ - TEST_VADDHN1(INSN, T1, T2, W, W2, N) - - DECL_VARIABLE_64BITS_VARIANTS(vector64); - DECL_VARIABLE_128BITS_VARIANTS(vector1); - DECL_VARIABLE_128BITS_VARIANTS(vector2); - - clean_results (); - - /* Fill input vector1 and vector2 with arbitrary values */ - VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1)); - VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1)); - VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1)); - VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1)); - VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1)); - VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1)); - - VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX); - VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX); - VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX); - VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX); - VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX); - VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX); - - TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8); - TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4); - TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2); - TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8); - TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4); - TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2); - - CHECK_RESULTS (TEST_MSG, ""); -} - -int main (void) -{ - FNNAME (INSN_NAME) (); - return 0; -} +#include "vXXXhn.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c new file mode 100644 index 0000000..6cd737c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c @@ -0,0 +1,58 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#if defined(__cplusplus) +#include +#else +#include +#endif + +#define INSN_NAME vraddhn +#define TEST_MSG "VRADDHN" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x19, 0x19 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x4, 0x4, 0x4, + 0x4, 0x4, 0x4, 0x4 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x38, 0x38, 0x38, 0x38 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x4, 0x4 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +#include "vXXXhn.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c new file mode 100644 index 0000000..9f0630d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c @@ -0,0 +1,58 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#if defined(__cplusplus) +#include +#else +#include +#endif + +#define INSN_NAME vrsubhn +#define TEST_MSG "VRSUBHN" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31, + 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x2, 0x2 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +#include "vXXXhn.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c new file mode 100644 index 0000000..b0b7893 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c @@ -0,0 +1,58 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#if defined(__cplusplus) +#include +#else +#include +#endif + +#define INSN_NAME vsubhn +#define TEST_MSG "VSUBHN" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31, + 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x2, 0x2 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +#include "vXXXhn.inc"