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[209.132.180.131]) by mx.google.com with ESMTPS id n14si9286001pfb.155.2016.12.03.09.30.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Dec 2016 09:30:48 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-443420-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-443420-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-443420-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=sIpp96gWrvRp4TRX g88YRuQoginouBB+AXVvOXHMKmJ8LHr2oeOYKlLSZstrLVtLhU4DcFvxiCNgf4+X zLawHKNRRUHUxtUWsRSHL1X2a8dFPv9oZfgfCMhGEUvHEIOtTlZfssQeOX1/oZIl bdwA4K/wMVEhpKo5SjoTyndkiQQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=04Ssl60KViyE5GIWsUB10L AOQSs=; b=xJ9ETAfIPo3wf8+gWR/gWAntDyzhTcMbFQ62qgcVqF0D9QlKZ8AyKx yR7PlQqJlUYmbJUgTZPu/GeMWWJa/qJDFKavjmaZg+0cqgGAP5ZvkT6A7q1EJ9am KV7YgXISRHxxqv/FQKQ0iNl6bJ8gaYeBOIg2vyLalvSFYH5okmIog= Received: (qmail 95095 invoked by alias); 3 Dec 2016 17:30:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 95000 invoked by uid 89); 3 Dec 2016 17:30:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=no version=3.3.2 spammy=ew, bonafide, eo, ou X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 03 Dec 2016 17:30:19 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 8848581308 for ; Sat, 3 Dec 2016 18:30:09 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IK84ab2pcpPR for ; Sat, 3 Dec 2016 18:30:09 +0100 (CET) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 55E7C81300 for ; Sat, 3 Dec 2016 18:30:09 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Disable U constraint with LRA Date: Sat, 03 Dec 2016 18:30:08 +0100 Message-ID: <10524940.hq2ygGAiKI@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-48-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 As diagnosed by DaveM, there is a bad interaction between the U constraint used by the SPARC port to represent "aligned" double-word registers in 32-bit mode and LRA; more precisely, LRA doesn't play as nice as reload with it because it's not declared with define_register_constraint. Fixed by disabling the relevant alternatives in the few patterns using the constraint and replacing it with a simple r constraint. This yields a clean C testsuite in 32-bit mode. The generated code seems to be slightly better than with reload, except for one issue: LRA doesn't seem to take into account the REG_ALLOC_ORDER specified by the architecture for picking reload registers, which means that it doesn't use leaf registers in leaf functions, which in turn blocks the leaf function optimization on SPARC. We cannot switch SPARC to LRA until after this is fixed, I'm going to open an enhancement PR. Tested on SPARC/Solaris, applied on the mainline. 2016-12-03 Eric Botcazou David S. Miller * config/sparc/constraints.md (U): Adjust comment. * config/sparc/sparc.md (lra): New attribute. (enabled): For base instructions, if the lra attribute is set, return 1 if it is in keeping with TARGET_LRA. (*movdi_insn_sp32): Add lra attribute for alternatives mentioning U constraint and duplicate them with U replaced by r. (*movdf_insn_sp32): Likewise. (*mov_insn_sp32): Likewise. (*movtf_insn_sp32): Remove alternatives mentioning U constraint. -- Eric Botcazou Index: config/sparc/constraints.md =================================================================== --- config/sparc/constraints.md (revision 243172) +++ config/sparc/constraints.md (working copy) @@ -166,10 +166,10 @@ (define_memory_constraint "T" ;; example, we have a non-offsetable MEM. Reload will notice this ;; case and reload the address into a single hard register. ;; -;; The real downfall of this awkward register constraint is that it does -;; not evaluate to a true register class like a bonafide use of -;; define_register_constraint would. This currently means that we cannot -;; use LRA on Sparc, since the constraint processing of LRA really depends +;; The real downfall of this awkward register constraint is that it +;; does not evaluate to a true register class like a bonafide use of +;; define_register_constraint would. This means that we cannot use +;; it with LRA, since the constraint processing of LRA really depends ;; upon whether an extra constraint is for registers or not. It uses ;; reg_class_for_constraint, and checks it against NO_REGS. (define_constraint "U" Index: config/sparc/sparc.md =================================================================== --- config/sparc/sparc.md (revision 243172) +++ config/sparc/sparc.md (working copy) @@ -254,8 +254,14 @@ (define_attr "isa" "v7,v8,v9,sparclet" (define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4" (const_string "none")) +(define_attr "lra" "none,disabled,enabled" + (const_string "none")) + (define_attr "enabled" "" - (cond [(eq_attr "cpu_feature" "none") (const_int 1) + (cond [(eq_attr "cpu_feature" "none") + (cond [(eq_attr "lra" "disabled") (symbol_ref "!TARGET_LRA") + (eq_attr "lra" "enabled") (symbol_ref "TARGET_LRA")] + (const_int 1)) (eq_attr "cpu_feature" "fpu") (symbol_ref "TARGET_FPU") (eq_attr "cpu_feature" "fpunotv9") (symbol_ref "TARGET_FPU && !TARGET_V9") (eq_attr "cpu_feature" "v9") (symbol_ref "TARGET_V9") @@ -1701,9 +1707,9 @@ (define_expand "movdi" (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b") + "=T,o,T,T,U,r,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b") (match_operand:DI 1 "input_operand" - " J,J,U,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))] + " J,J,U,r,T,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))] "TARGET_ARCH32 && (register_operand (operands[0], DImode) || register_or_zero_operand (operands[1], DImode))" @@ -1711,6 +1717,8 @@ (define_insn "*movdi_insn_sp32" stx\t%%g0, %0 # std\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 ldd\t%1, %0 # # @@ -1728,11 +1736,12 @@ (define_insn "*movdi_insn_sp32" std\t%1, %0 fzero\t%0 fone\t%0" - [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,*,*,*,fpload,fpstore,visl,visl") - (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,2,2,2,*,*,*,*") - (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double") - (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis") - (set_attr "v3pipe" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,true,true")]) + [(set_attr "type" "store,store,store,store,load,load,*,*,*,*,fpstore,fpload,*,*,fpmove,*,*,*,fpload,fpstore,visl,visl") + (set_attr "length" "*,2,*,*,*,*,2,2,2,2,*,*,2,2,*,2,2,2,*,*,*,*") + (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double") + (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis") + (set_attr "v3pipe" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,true,true") + (set_attr "lra" "*,*,disabled,enabled,disabled,enabled,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")]) (define_insn "*movdi_insn_sp64" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, r,*e,?*e,?*e,?W,b,b") @@ -2372,9 +2381,9 @@ (define_expand "movdf" (define_insn "*movdf_insn_sp32" [(set (match_operand:DF 0 "nonimmediate_operand" - "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o") + "=b,b,e,e,*r, f, e,T,W,U,r,T,T, f, *r, o,o") (match_operand:DF 1 "input_operand" - " G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))] + " G,C,e,e, f,*r,W#F,G,e,T,T,U,r,o#F,*roF,*rG,f"))] "TARGET_ARCH32 && (register_operand (operands[0], DFmode) || register_or_zero_or_all_ones_operand (operands[1], DFmode))" @@ -2389,16 +2398,19 @@ (define_insn "*movdf_insn_sp32" stx\t%r1, %0 std\t%1, %0 ldd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 std\t%1, %0 # # # #" - [(set_attr "type" "visl,visl,fpmove,*,*,*,fpload,store,fpstore,load,store,*,*,*,*") - (set_attr "length" "*,*,*,2,2,2,*,*,*,*,*,2,2,2,2") - (set_attr "fptype" "double,double,double,*,*,*,*,*,*,*,*,*,*,*,*") - (set_attr "cpu_feature" "vis,vis,v9,fpunotv9,vis3,vis3,fpu,v9,fpu,*,*,fpu,*,*,fpu") - (set_attr "v3pipe" "true,true,*,*,*,*,*,*,*,*,*,*,*,*,*")]) + [(set_attr "type" "visl,visl,fpmove,*,*,*,fpload,store,fpstore,load,load,store,store,*,*,*,*") + (set_attr "length" "*,*,*,2,2,2,*,*,*,*,*,*,*,2,2,2,2") + (set_attr "fptype" "double,double,double,*,*,*,*,*,*,*,*,*,*,*,*,*,*") + (set_attr "cpu_feature" "vis,vis,v9,fpunotv9,vis3,vis3,fpu,v9,fpu,*,*,*,*,fpu,*,*,fpu") + (set_attr "v3pipe" "true,true,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*") + (set_attr "lra" "*,*,*,*,*,*,*,*,*,disabled,enabled,disabled,enabled,*,*,*,*")]) (define_insn "*movdf_insn_sp64" [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,*r, e, e,W, *r,*r, m,*r") @@ -2609,14 +2621,14 @@ (define_expand "movtf" }) (define_insn "*movtf_insn_sp32" - [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,U, r") - (match_operand:TF 1 "input_operand" " G,oe,e,rGU,o,roG"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o, r") + (match_operand:TF 1 "input_operand" " G,oe,e,rG,roG"))] "TARGET_ARCH32 && (register_operand (operands[0], TFmode) || register_or_zero_operand (operands[1], TFmode))" "#" - [(set_attr "length" "4,4,4,4,4,4") - (set_attr "cpu_feature" "fpu,fpu,fpu,*,*,*")]) + [(set_attr "length" "4,4,4,4,4") + (set_attr "cpu_feature" "fpu,fpu,fpu,*,*")]) (define_insn "*movtf_insn_sp64" [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o, r") @@ -8636,8 +8648,8 @@ (define_insn "*mov_insn_sp64" (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,*,*")]) (define_insn "*mov_insn_sp32" - [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,T, o,*r") - (match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,U,*r,*r"))] + [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,r,T,T, o,*r") + (match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,T,U,r,*r,*r"))] "TARGET_VIS && TARGET_ARCH32 && (register_operand (operands[0], mode) @@ -8652,13 +8664,16 @@ (define_insn "*mov_insn_sp32" std\t%1, %0 stx\t%r1, %0 ldd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 std\t%1, %0 # #" - [(set_attr "type" "visl,visl,vismv,*,*,fpload,fpstore,store,load,store,*,*") - (set_attr "length" "*,*,*,2,2,*,*,*,*,*,2,2") - (set_attr "cpu_feature" "vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*") - (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,*,*,*")]) + [(set_attr "type" "visl,visl,vismv,*,*,fpload,fpstore,store,load,load,store,store,*,*") + (set_attr "length" "*,*,*,2,2,*,*,*,*,*,*,*,2,2") + (set_attr "cpu_feature" "vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*,*,*") + (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,*,*,*,*,*") + (set_attr "lra" "*,*,*,*,*,*,*,*,disabled,enabled,disabled,enabled,*,*")]) (define_split [(set (match_operand:VM64 0 "memory_operand" "")