From patchwork Wed Feb 21 09:20:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 128997 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp409203ljc; Wed, 21 Feb 2018 01:21:04 -0800 (PST) X-Google-Smtp-Source: AH8x226C96g5bR6HLzD7QhzWVc3dR4iy9WywtA0AMBZhBBolztYDUbSZVmdBe+p6fCXvNLtoXby9 X-Received: by 10.99.142.76 with SMTP id k73mr2195151pge.278.1519204864590; Wed, 21 Feb 2018 01:21:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519204864; cv=none; d=google.com; s=arc-20160816; b=KiioGvim1icjLTN/F2ihPQmwRxgRR2XMASmQWCdZNVH0f60dY+sSniXKUPqx+3HCnU hewM/6Yczb+SjlWHWiMgun+lc1KfKjP3zt77cOjn4HdJ0MOH6FgYUPh0h0YyFc6i9N7I IDKQFdLta27mBhZtCYqXU6nrwI0t4wkvY6D2G87yPpy2D/ENVPyAnB+u4dd/m51pJ/an oI46elmKx9sludV9pOcnOMJ67izW9W4WLxHkJzJKIqiNoKgbpjA/s3gK4AHGhLfHZ7Nc dxoEidOo031q4BntvGWC8AuCbC/BdtHrAgk3iCGobw4kfhVVz7HCgDeU2P28cxA+CUyM hNQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:references:in-reply-to:references:in-reply-to :message-id:date:subject:to:from:delivered-to :arc-authentication-results; bh=SRCLkXA3FDqcMC7+xs5kCB7Ru6EeY12g3WXFZv+1R0s=; b=bHSo7bJyt6c81dA2UUQU8BDqXdjFAY7fglfltvy8SyNGCB+t0QKymCWQOntC8T0ZCX rVK4ZhHSH/wV/zBBnvObcTzRk5nhmVdymlMW41VOSWYrrrWATiZ2lc8qTt5nDmD+/oPy Bsl70B57XvR/quKBLnZqjzrH2R/ld8K5+YImUIoqfJwvT3r+S1ShZftAXUR4QS03552F 3diZlCOtl/AMwp7gkI3z6mvHGYtLq4SoFkfvdeYMcWuo7TjeM24QKVsZHTW/EI7CS4ab IGm5V2BpFX1uqAG5MEy4ZWEWUAu0CdrbLEKB/TuL/1iMdx6Sjqo3O6+oYvCRLraBSYAp 3jEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id k15si955816pgc.482.2018.02.21.01.21.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Feb 2018 01:21:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E93076E59C; Wed, 21 Feb 2018 09:21:01 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54]) by gabe.freedesktop.org (Postfix) with ESMTP id D9E2D6E59C for ; Wed, 21 Feb 2018 09:21:00 +0000 (UTC) Received: by mail.free-electrons.com (Postfix, from userid 110) id 95B4D207D7; Wed, 21 Feb 2018 10:20:59 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id B029A207E4; Wed, 21 Feb 2018 10:20:40 +0100 (CET) From: Maxime Ripard To: Mark Brown , Thierry Reding , Chen-Yu Tsai , Maxime Ripard , Mark Rutland , Rob Herring Subject: [PATCH v2 04/10] dt-bindings: display: Add Allwinner MIPI-DSI bindings Date: Wed, 21 Feb 2018 10:20:28 +0100 Message-Id: X-Mailer: git-send-email 2.14.3 In-Reply-To: References: In-Reply-To: References: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Thomas Petazzoni , Daniel Vetter , Maxime Ripard , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Maxime Ripard The Allwinner SoCs usually come with a DSI encoder. Add a binding for it. Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 84 +++++++- 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt new file mode 100644 index 000000000000..cbcc673b9bcc --- /dev/null +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt @@ -0,0 +1,84 @@ +Allwinner A31 DSI Encoder +========================= + +The DSI pipeline consists of two separate blocks: the DSI controller +itself, and its associated D-PHY. + +DSI Encoder +----------- + +The DSI Encoder generates the DSI signal from the TCON's. + +Required properties: + - compatible: value must be one of: + * allwinner,sun6i-a31-mipi-dsi + - reg: base address and size of memory-mapped region + - interrupts: interrupt associated to this IP + - clocks: phandles to the clocks feeding the DSI encoder + * bus: the DSI interface clock + * mod: the DSI module clock + - clock-names: the clock names mentioned above + - phys: phandle to the D-PHY + - phy-names: must be "dphy" + - resets: phandle to the reset controller driving the encoder + + - ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + port should be the input endpoint, usually coming from the + associated TCON. + +Any MIPI-DSI device attached to this should be described according to +the bindings defined in ../mipi-dsi-bus.txt + +D-PHY +----- + +Required properties: + - compatible: value must be one of: + * allwinner,sun6i-a31-mipi-dphy + - reg: base address and size of memory-mapped region + - clocks: phandles to the clocks feeding the DSI encoder + * bus: the DSI interface clock + * mod: the DSI module clock + - clock-names: the clock names mentioned above + - resets: phandle to the reset controller driving the encoder + +Example: + +dsi0: dsi@1ca0000 { + compatible = "allwinner,sun6i-a31-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy0>; + phy-names = "dphy"; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "huarui,lhr050h41"; + reg = <0>; + power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */ + reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ + backlight = <&pwm_bl>; + }; + + port { + dsi0_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi0>; + }; + }; +}; + +dphy0: d-phy@1ca1000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + #phy-cells = <0>; +};