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[131.252.210.177]) by mx.google.com with ESMTPS id d76si5569281pga.329.2018.02.16.03.25.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Feb 2018 03:25:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=pD09E5m2; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61BBE6E014; Fri, 16 Feb 2018 11:25:22 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F3D36E014 for ; Fri, 16 Feb 2018 11:25:21 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w1GBPISx025106; Fri, 16 Feb 2018 05:25:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518780318; bh=ERUy6FWZkCJnu5i97yIt2AX58kClUDA9OPL1safNvcQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pD09E5m23tQaRf3PIulBuTiIM4SH1HdcOCTCtZppjIGHZ79tQ7vM3LcXZWfegFL6q yKKnAGzpbrVNiewmpwyNVnFWXmYdHU3mBvBeQOYJy7ylb0kknbb9KXeEmuFzlNf7bb pJnzwlcnS1lNbuqnW8V3CTpz9z/uy2pBlg8hOYYY= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1GBPIG6003616; Fri, 16 Feb 2018 05:25:18 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 16 Feb 2018 05:25:18 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 16 Feb 2018 05:25:18 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1GBPCif028841; Fri, 16 Feb 2018 05:25:17 -0600 From: Jyri Sarha To: , , Subject: [PATCH RFC 3/9] drm/omap: Add ovl_name() and mgr_name() to dispc_ops Date: Fri, 16 Feb 2018 13:25:04 +0200 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add ovl_name() and mgr_name() to dispc_ops and get rid of adhoc names here and there in the omapdrm code. This moves the names of hardware entities to omapdss side where they have to be when new omapdss backend drivers are introduced. Signed-off-by: Jyri Sarha Reviewed-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 5 +++++ drivers/gpu/drm/omapdrm/omap_crtc.c | 11 ++--------- drivers/gpu/drm/omapdrm/omap_irq.c | 19 +++++++------------ drivers/gpu/drm/omapdrm/omap_plane.c | 13 +++---------- 5 files changed, 40 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 338490d..6f83b3e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -694,6 +694,26 @@ void dispc_runtime_put(struct dispc_device *dispc) WARN_ON(r < 0 && r != -ENOSYS); } +static const char *dispc_ovl_name(struct dispc_device *dispc, + enum omap_plane_id plane) +{ + static const char * const ovl_names[] = { + [OMAP_DSS_GFX] = "GFX", + [OMAP_DSS_VIDEO1] = "VID1", + [OMAP_DSS_VIDEO2] = "VID2", + [OMAP_DSS_VIDEO3] = "VID3", + [OMAP_DSS_WB] = "WB", + }; + + return ovl_names[plane]; +} + +static const char *dispc_mgr_name(struct dispc_device *dispc, + enum omap_channel channel) +{ + return mgr_desc[channel].name; +} + static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, enum omap_channel channel) { @@ -4662,6 +4682,9 @@ static const struct dispc_ops dispc_ops = { .get_num_ovls = dispc_get_num_ovls, .get_num_mgrs = dispc_get_num_mgrs, + .ovl_name = dispc_ovl_name, + .mgr_name = dispc_mgr_name, + .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit, .mgr_enable = dispc_mgr_enable, diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 1299dd6..b84cfd8 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -711,6 +711,11 @@ struct dispc_ops { int (*get_num_ovls)(struct dispc_device *dispc); int (*get_num_mgrs)(struct dispc_device *dispc); + const char *(*ovl_name)(struct dispc_device *dispc, + enum omap_plane_id plane); + const char *(*mgr_name)(struct dispc_device *dispc, + enum omap_channel channel); + u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc); void (*mgr_enable)(struct dispc_device *dispc, diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 6c4d40b..00ec959 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -672,13 +672,6 @@ static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { * Init and Cleanup */ -static const char *channel_names[] = { - [OMAP_DSS_CHANNEL_LCD] = "lcd", - [OMAP_DSS_CHANNEL_DIGIT] = "tv", - [OMAP_DSS_CHANNEL_LCD2] = "lcd2", - [OMAP_DSS_CHANNEL_LCD3] = "lcd3", -}; - void omap_crtc_pre_init(struct omap_drm_private *priv) { memset(omap_crtcs, 0, sizeof(omap_crtcs)); @@ -706,7 +699,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, channel = out->dispc_channel; omap_dss_put_device(out); - DBG("%s", channel_names[channel]); + DBG("%s", priv->dispc_ops->mgr_name(priv->dispc, channel)); /* Multiple displays on same channel is not allowed */ if (WARN_ON(omap_crtcs[channel] != NULL)) @@ -721,7 +714,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, init_waitqueue_head(&omap_crtc->pending_wait); omap_crtc->channel = channel; - omap_crtc->name = channel_names[channel]; + omap_crtc->name = priv->dispc_ops->mgr_name(priv->dispc, channel); ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, &omap_crtc_funcs, NULL); diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index c8511504..5cc88b6 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -146,15 +146,10 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv, { static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); - static const struct { - const char *name; - u32 mask; - } sources[] = { - { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, - { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW }, - { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW }, - { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW }, - }; + static const u32 irqbits[] = { DISPC_IRQ_GFX_FIFO_UNDERFLOW, + DISPC_IRQ_VID1_FIFO_UNDERFLOW, + DISPC_IRQ_VID2_FIFO_UNDERFLOW, + DISPC_IRQ_VID3_FIFO_UNDERFLOW }; const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW | DISPC_IRQ_VID1_FIFO_UNDERFLOW @@ -174,9 +169,9 @@ static void omap_irq_fifo_underflow(struct omap_drm_private *priv, DRM_ERROR("FIFO underflow on "); - for (i = 0; i < ARRAY_SIZE(sources); ++i) { - if (sources[i].mask & irqstatus) - pr_cont("%s ", sources[i].name); + for (i = 0; i < ARRAY_SIZE(irqbits); ++i) { + if (irqbits[i] & irqstatus) + pr_cont("%s ", priv->dispc_ops->ovl_name(priv->dispc, i)); } pr_cont("(0x%08x)\n", irqstatus); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 2899435..61b0753 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -239,13 +239,6 @@ static const struct drm_plane_funcs omap_plane_funcs = { .atomic_get_property = omap_plane_atomic_get_property, }; -static const char *plane_id_to_name[] = { - [OMAP_DSS_GFX] = "gfx", - [OMAP_DSS_VIDEO1] = "vid1", - [OMAP_DSS_VIDEO2] = "vid2", - [OMAP_DSS_VIDEO3] = "vid3", -}; - static const enum omap_plane_id plane_idx_to_id[] = { OMAP_DSS_GFX, OMAP_DSS_VIDEO1, @@ -272,7 +265,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, id = plane_idx_to_id[idx]; - DBG("%s: type=%d", plane_id_to_name[id], type); + DBG("%s: type=%d", priv->dispc_ops->ovl_name(priv->dispc, id), type); omap_plane = kzalloc(sizeof(*omap_plane), GFP_KERNEL); if (!omap_plane) @@ -282,7 +275,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, for (nformats = 0; formats[nformats]; ++nformats) ; omap_plane->id = id; - omap_plane->name = plane_id_to_name[id]; + omap_plane->name = priv->dispc_ops->ovl_name(priv->dispc, id); plane = &omap_plane->base; @@ -301,7 +294,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, error: dev_err(dev->dev, "%s(): could not create plane: %s\n", - __func__, plane_id_to_name[id]); + __func__, priv->dispc_ops->ovl_name(priv->dispc, id)); kfree(omap_plane); return NULL;