From patchwork Tue Oct 16 14:06:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 148944 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5137264lji; Tue, 16 Oct 2018 07:06:57 -0700 (PDT) X-Google-Smtp-Source: ACcGV63T+CrbpCOPuAhnVJCfzBlVHxY5DDbFxBBdCH0IYJFwVwivbOMrXJ6b0edToVPvvImQx2Ol X-Received: by 2002:a63:6a86:: with SMTP id f128-v6mr20643032pgc.165.1539698817019; Tue, 16 Oct 2018 07:06:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539698817; cv=none; d=google.com; s=arc-20160816; b=h5z2utKsDZ8DGPf8wMZOvIFX8SVGSHiREfuhYZ32+Hrls0e+2b8Uw4ElYt9b4caneK /QcqYF7gOi2EOfc9I0bVvVmMrm7EcZB1zuTYemVUyq5Dl2sj5Cz1N44caLe2sPHqE2Kt qIHveOztCi79lhDwjuH4yU7BS6C4P2Oo8ztyjwZeMWZT1woJgJNd7QfxN6f/mhIJR3IH KNQDHJo3JNIs749/6hO0b3jroPQXlCYKOcHQznNYXtdD0WYZDyMlsxZDlorSbc6+Fjk+ 14eY28pCZBGRHWfSvA0X27zAknegzPzPBmHffV4bUOq2F6FWiTxEWGxBKbDRYL2zP9Il 0lAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:to :subject:message-id:date:from:mime-version:delivered-to; bh=uOHrh/3rB4TmxD9Ql4muHRMbirAqMj1X5QF0dACY3x8=; b=keoOLqxGEVwXJw9MRn5CnY8uHxm3Z8RDFUrZPVYwbEFTYXzURa43cSwTIjEQLOQK/M JlAdxdT23n5oIG56Fng2ESnIfgZ+y9F+WgXjG/v/oiwAb4Sm3I0pUXK1NQtwLY+pSCKi s+7dbq0KDveOYG78e6j4vZ5KfN3XpEloYEErIR8ey119lgi5wC9ybjtNAB1fZ73sZQob NpkDipfMPwVbUykocrs/HERkf1C53Zt50NygpOmAgLC49g3nLYhiURo+8uxqS53hWtAR HvPXCIpSbuLLBmoFJFfqlxo5lZD5Z0x9or2Pjs6XAaKddoY5lmISOyNc8Wv1HRju2RDz 841Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id n6-v6si14118386pgr.150.2018.10.16.07.06.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 07:06:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B67806E238; Tue, 16 Oct 2018 14:06:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qk1-x744.google.com (mail-qk1-x744.google.com [IPv6:2607:f8b0:4864:20::744]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6020A6E238 for ; Tue, 16 Oct 2018 14:06:24 +0000 (UTC) Received: by mail-qk1-x744.google.com with SMTP id p6-v6so14200313qkg.1 for ; Tue, 16 Oct 2018 07:06:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=IHmA9/EmWgyNJ/j0tH5pwV2vKtHCsdnc+Kpq2lRGI6w=; b=HZSEJjCRGMfjlnR5+HV1YP1Fw7Sudg9mjZB9KeC/0BgyyZBnlTgsNvxfPPOB9Zap6q WeqCw7p9fGkesb7qX45eBL6subuJPS9rrVXBX6gM87ua4UcSl/q42Dz5LRCUy4RYqFU2 1a3EUin+zfspytJax4/LQi960KpCZcG2HuXf1Ic33sa8jsTqLibihVAHaHSIvzxRS8JS Vm+idm8cxxjEvT3IrBU+56UZc8dUmeIDWQ0g0bLZko5/ez7GX3XMELMatnyXzhIWw/Af roQjCVhMLbQ5/s978U2XYvZt2SBh/A7tm/CprLI1eongp01DkzcyWepH1R3oSjVSusZb b2AQ== X-Gm-Message-State: ABuFfojM2tReKSSUpBlbEiyZQF49tUQLeVUAt4s66At6KOpc+KQjJ5XP imzASnaxab41iLDd0N9o81l0iFEw2gHGcrob9uLpWw== X-Received: by 2002:a37:1f53:: with SMTP id f80-v6mr19783700qkf.109.1539698783398; Tue, 16 Oct 2018 07:06:23 -0700 (PDT) MIME-Version: 1.0 From: Linus Walleij Date: Tue, 16 Oct 2018 16:06:10 +0200 Message-ID: Subject: RFC: DSI panel lane frequency To: Andrzej Hajda , "open list:DRM PANEL DRIVERS" , Thierry Reding , Vinay Simha BN , Archit Taneja , Chandan Uddaraju X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi folks, I just randomly add some people that committed code to the DSI core so I can get some reasonable feedback. I started looking at some DSI drivers I'm adding and it seems this platform (Ux500 MCDE) can control the bus frequency of the DSI interface. It can be controlled independently for command and video mode, and there is an LP (low power) frequency and a HS (high speed) frequency for the lane. The MIPI specification seems to say "The maximum Lane frequency shall be documented by the DSI device manufacturer." Then it goes on to specify tolerance for the HS and LP frequency. So apparently those are not standard frequencies. I was thinking to add something like this: LS/HS frequency? (If zero, we could assume some default I guess.) Yours, Linus Walleij diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 4fef19064b0f..9c78eb78b027 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -168,6 +168,8 @@ struct mipi_dsi_device_info { * @format: pixel format for video mode * @lanes: number of active data lanes * @mode_flags: DSI operation mode related flags + * @hs_frequency: Maximum frequency for high speed operation + * @lp_frequency: Maximum frequency for low power operation */ struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -178,6 +180,8 @@ struct mipi_dsi_device { unsigned int lanes; enum mipi_dsi_pixel_format format; unsigned long mode_flags; + unsigned long hs_frequency; + unsigned long lp_frequency; }; Is this what we should do to make DSI panels expose their max