From patchwork Tue Nov 16 06:22:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 519185 Delivered-To: patch@linaro.org Received: by 2002:ac0:c605:0:0:0:0:0 with SMTP id p5csp6710817imj; Mon, 15 Nov 2021 22:24:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJw6BdvTSSaZyKzhxSrZGqJ/A2X8+kTtxEN/bkb0/FEZMTqkRoYw9KKxH7BpLHqxN9vN/Lca X-Received: by 2002:a05:6a00:1399:b0:49f:ae7d:cda6 with SMTP id t25-20020a056a00139900b0049fae7dcda6mr38232023pfg.10.1637043846604; Mon, 15 Nov 2021 22:24:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1637043846; cv=none; d=google.com; s=arc-20160816; b=hnHkh7NWhukzoaZOQcOQBkpzRfUQsMRkQ//twLngQxDKHHDTSmlswxjExIpxn7gp7H g1fUHWFwX1d+SjKYVIegsTiSnPhT0s0lIOCRVSJbiVT+sAjWHHlo4fpq/QzZctC0RvZP WDm0U+hnlt5omWIqfHbEvGAJux14nFBD/1i3pkJzN3nGakJApkMRizdsV3D71kCw5SdN lXt6mMVD2RKxYcNHtaPQNR+6ev4U0KfvedtW39QSn14OGI+yzaPMugWOBvAr7qMgX7n0 VIlVBOAVWEYhxx7PTEq6vqB+aby7J8nRymc1YJ2/GsAkezYsp3oDEoF2lpVgfT0batS6 eFGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:delivered-to; bh=3kQ412mM6+oS6f+927xW3cHnK0nnFsB+9EEEJ6nqW8s=; b=gjDGRc6B9DSjthKz3uGiY63uTfYs8m9VsK5yv8tH51vFUQwApY423Nh6sP0SEF1evW RX8xgxZMGm7V/pakKUwx6pfVwUfNtNdPxBjfmHaekD5O8Dhr8I3gC6oy4fQnQiNDNLxY tlK6b68gWbXQ0j0COXiOgEVrOhWEajMplCm5xU30kgAVmiZW4moqwN774+0h/QlAwXnE qQ3TDaHwOKQsDVU+utWShiATr2QXRbwcfPgTgzh8QVWd6AmRdLo5GBFGaiPjfN3wIjWD +eKWr+uNKU8tllnsKNf2J8xvCUlkcv8qe9y+kOzFTNdo2umV3hsnydkW7zXMbMYrbPMN Qj2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=is005f1c; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id i69si11393039pge.566.2021.11.15.22.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 22:24:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=is005f1c; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A8576ED9D; Tue, 16 Nov 2021 06:24:05 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2735F6ED9F; Tue, 16 Nov 2021 06:24:04 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 8845961A0D; Tue, 16 Nov 2021 06:23:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637043844; bh=Rdi335vDsE1+78XelWCe9wjnVj1n/u/4sMFTdqlkam0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=is005f1cpZ4F5n/0J+buG2g+RDZdrlA0rydZHEIHCUJSYkyFQQ2cjG+mFTtz9xZmi amaSzfEWV3U/4y38jgx4H1uBkvNzOjsI/nB8syz0+1CbMllt/nj9PA7m0c/qRBIChr u0FyJgmUYX5spQNr6KdRw+QrG/yB9O295U33sjaewfA2S83PpWsynWUy3nJS8E5TxD LdEcuiv5UFsPa7YOaCMqT7LxLk9cSUVvXKd8dW7VQ3juy1H2T/gp8W/ZfQbt/eUSiR qrCnpT334dXYd6N0cF9zWE4ieSl2Dx9n7hpWGagFUvB6uAfZLmZLap2aq9jwcS8h6D txZz5HivHShAw== From: Vinod Koul To: Rob Clark Subject: [PATCH v3 10/13] drm/msm/disp/dpu1: Add DSC support in RM Date: Tue, 16 Nov 2021 11:52:53 +0530 Message-Id: <20211116062256.2417186-11-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211116062256.2417186-1-vkoul@kernel.org> References: <20211116062256.2417186-1-vkoul@kernel.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , Jeffrey Hugo , David Airlie , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Bjorn Andersson , Vinod Koul , dri-devel@lists.freedesktop.org, Dmitry Baryshkov , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This add the bits in RM to enable the DSC blocks Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 66 +++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + 3 files changed, 68 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 775bcbda860f..fd6672efb096 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -146,6 +146,7 @@ struct dpu_global_state { uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f9c83d6e427a..c9d0fc765aaf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -11,6 +11,7 @@ #include "dpu_hw_intf.h" #include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" +#include "dpu_hw_dsc.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_intf_destroy(hw); } } + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) { + struct dpu_hw_dsc *hw; + + if (rm->dsc_blks[i]) { + hw = to_dpu_hw_dsc(rm->dsc_blks[i]); + dpu_hw_dsc_destroy(hw); + } + } return 0; } @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm, rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; } + for (i = 0; i < cat->dsc_count; i++) { + struct dpu_hw_dsc *hw; + const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; + + hw = dpu_hw_dsc_init(dsc->id, mmio, cat); + if (IS_ERR_OR_NULL(hw)) { + rc = PTR_ERR(hw); + DPU_ERROR("failed dsc object creation: err %d\n", rc); + goto fail; + } + rm->dsc_blks[dsc->id - DSC_0] = &hw->base; + } + return 0; fail: @@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf( } global_state->intf_to_enc_id[idx] = enc_id; + return 0; } @@ -500,6 +523,38 @@ static int _dpu_rm_reserve_intf_related_hw( return ret; } +static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_encoder *enc, + const struct msm_display_topology *top) +{ + struct msm_drm_private *priv; + int num_dsc = top->num_dsc; + int i; + + priv = enc->dev->dev_private; + + if (!priv) + return -EIO; + + /* check if DSC is supported */ + if (!priv->dsc) + return 0; + + /* check if DSC required are allocated or not */ + for (i = 0; i < num_dsc; i++) { + if (global_state->dsc_to_enc_id[i]) { + DPU_ERROR("DSC %d is already allocated\n", i); + return -EIO; + } + } + + for (i = 0; i < num_dsc; i++) + global_state->dsc_to_enc_id[i] = enc->base.id; + + return 0; +} + static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, @@ -526,6 +581,10 @@ static int _dpu_rm_make_reservation( if (ret) return ret; + ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology); + if (ret) + return ret; + return ret; } @@ -567,6 +626,8 @@ void dpu_rm_release(struct dpu_global_state *global_state, ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->intf_to_enc_id, ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id); + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); } int dpu_rm_reserve( @@ -640,6 +701,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, hw_to_enc_id = global_state->dspp_to_enc_id; max_blks = ARRAY_SIZE(rm->dspp_blks); break; + case DPU_HW_BLK_DSC: + hw_blks = rm->dsc_blks; + hw_to_enc_id = global_state->dsc_to_enc_id; + max_blks = ARRAY_SIZE(rm->dsc_blks); + break; default: DPU_ERROR("blk type %d not managed by rm\n", type); return 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..278d2a510b80 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -30,6 +30,7 @@ struct dpu_rm { struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; uint32_t lm_max_width; };