From patchwork Fri May 21 12:49:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444682 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp947332jac; Fri, 21 May 2021 05:50:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw+CeGdbAUmz7UiS1o/pbFIhrapwm89OjJML2ix0veK1DJG4SyC/cRAph7WZv5fds4zlYQo X-Received: by 2002:a63:6383:: with SMTP id x125mr9801407pgb.161.1621601459560; Fri, 21 May 2021 05:50:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621601459; cv=none; d=google.com; s=arc-20160816; b=aOw5UqPFwRsReokZyW2SR6XX5Oko8ntlz+YMtgWI2J3ZzNHMWQZvvY1e4GxkyRkt9+ /SCdaznvj1u/D4y9AwR+uYClVSifKvqSEUwwCpG1Zv9nepY5pcUxpOm3JaV+3pIxEbFd xhHObw2wSupiPoZsNthqZ8B9PHrrPH1TVnhjDYS1dTPK3D5aY3tOG3+o6u1V9DDAjQFW O1+ErdkEqb1KOnHjY41Ugywmc18XUry3g0nA/mH0Vd6qsdJCl+UQNn5vzRtwGvcNwZzl f+UDTu2aPGKSK/cG0Okp1qMhnvXEWc08cMpMCCp5jgh+eKMZzrfr1kX/LEBFTgSdeI6O erBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:delivered-to; bh=J4oI+Klq7PXjhDoyPjalXgJwkXltU2p/kbThMSekDSk=; b=d8a4luP8U/i6wl7WYcghdcui5GlCie/oa7mDoniEBXr44HlH1cxVzJT5/rwLNZlnsw BdYoPoZgSH8vOKGRL0cWJZDvU05+YTXd2gwMfdOGTFM5+OpIRgCyjIAyw+un7ZeyGWK8 xhuvbJT+Z2XUMavrlCM6Qr9/25Xi14LIspLsOU/jrWDfhHJOOU6vuAym0q1EkaS8qhjy 0SpwCsxm05NCcTs98Auv8Arv2VjSA3av2mrUEF1q3Pb2pbVb9M+fPIlo9JAAonLyjATf snXoJzcsEYWXnR/GNmtShCmtGelzpeApmWjR1bcW6u005dgzaeBZNzuboHc46w7JaLyu FThQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=Ez8g6zKI; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id 62si7033280plb.203.2021.05.21.05.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 05:50:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=Ez8g6zKI; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 34A4E6F63D; Fri, 21 May 2021 12:50:58 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 07D716F63D; Fri, 21 May 2021 12:50:57 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 17FE4613DD; Fri, 21 May 2021 12:50:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601456; bh=Y6oR0c4fZFzazX3E5d47MSfaK8VBELYA/cqVKr86K0Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ez8g6zKIWFa0iXr/TmnV7hC8yycw1QjLElWJHhL1qeADa6euFZ/OqxcqDBcwn6Q2z yzdWzDqFy5C7gHcyEJKbIKL1Rq6nvwyyGwHypQfo4afjU/qEWTNPvCq6E0r0x+CLuw KlwKC4v0yEiTHqg2Qzo9/kSs/fbg+/DnF3Lq11Zyezjoj4bn9zSy5WTqZRJwnGLxWK OEMOlDYWa8sxOeAy2l5Bt1S/61hhLPGyXgFHMEa8pY2FrnqTM15IlBAwQEuEYBKp7Z FHwDW2lGghykiaA+aBNAyadcurEvTzTDzSRQ9g7jd90YacpvZ+MLH+bhYojIc2kWs1 +NIiX1KV6QoEQ== From: Vinod Koul To: Rob Clark Subject: [RFC PATCH 09/13] drm/msm/disp/dpu1: Dont use DSC with mode_3d Date: Fri, 21 May 2021 18:19:42 +0530 Message-Id: <20210521124946.3617862-14-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , David Airlie , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Bjorn Andersson , Vinod Koul , dri-devel@lists.freedesktop.org, Dmitry Baryshkov , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We cannot enable mode_3d when we are using the DSC. So pass configuration to detect DSC is enabled and not enable mode_3d when we are using DSC We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc enabled and pass this to .setup_intf_cfg() Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ 4 files changed, 18 insertions(+), 2 deletions(-) -- 2.26.3 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index ecbc4be98980..d43b804528eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -336,6 +336,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( return BLEND_3D_NONE; } +static inline bool dpu_encoder_helper_get_dsc_mode(struct dpu_encoder_phys *phys_enc) +{ + struct drm_encoder *drm_enc = phys_enc->parent; + struct msm_drm_private *priv = drm_enc->dev->dev_private; + + if (priv->dsc) + return true; + + return false; +} + /** * dpu_encoder_helper_split_config - split display configuration helper function * This helper function may be used by physical encoders to configure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b2be39b9144e..5fe87881c30c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -69,6 +69,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; intf_cfg.stream_sel = cmd_enc->stream_sel; intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); + intf_cfg.dsc = dpu_encoder_helper_get_dsc_mode(phys_enc); + ctl->ops.setup_intf_cfg(ctl, &intf_cfg); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index aeea6add61ee..f059416311ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -121,7 +121,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) return ctx->pending_flush_mask; } -static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) +static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3)); @@ -522,7 +522,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, intf_cfg |= (cfg->intf & 0xF) << 4; - if (cfg->mode_3d) { + /* In DSC we can't set merge, so check for dsc too */ + if (cfg->mode_3d && !cfg->dsc) { intf_cfg |= BIT(19); intf_cfg |= (cfg->mode_3d - 0x1) << 20; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 806c171e5df2..347a653c1e01 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg { * @mode_3d: 3d mux configuration * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid + * @dsc: DSC is enabled * @stream_sel: Stream selection for multi-stream interfaces */ struct dpu_hw_intf_cfg { @@ -46,6 +47,7 @@ struct dpu_hw_intf_cfg { enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; + bool dsc; int stream_sel; };