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Tue, 24 Nov 2020 11:44:17 -0800 (PST) Received: from dell.default ([91.110.221.235]) by smtp.gmail.com with ESMTPSA id d134sm200511wmd.8.2020.11.24.11.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Nov 2020 11:44:16 -0800 (PST) From: Lee Jones To: lee.jones@linaro.org Subject: [PATCH 15/40] drm/amd/amdgpu/gfx_v8_0: Functions must follow directly after their headers Date: Tue, 24 Nov 2020 19:37:59 +0000 Message-Id: <20201124193824.1118741-16-lee.jones@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201124193824.1118741-1-lee.jones@linaro.org> References: <20201124193824.1118741-1-lee.jones@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, =?utf-8?q?Christian_K=C3=B6nig?= , linaro-mm-sig@lists.linaro.org, dri-devel@lists.freedesktop.org, Alex Deucher , linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:3698: warning: Excess function parameter 'adev' description in 'DEFAULT_SH_MEM_BASES' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org Cc: linaro-mm-sig@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 5e6d15f44560a..9a905531f8377 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3687,6 +3687,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) mutex_unlock(&adev->grbm_idx_mutex); } +#define DEFAULT_SH_MEM_BASES (0x6000) /** * gfx_v8_0_init_compute_vmid - gart enable * @@ -3695,7 +3696,6 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) * Initialize compute vmid sh_mem registers * */ -#define DEFAULT_SH_MEM_BASES (0x6000) static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) { int i;