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[131.252.210.177]) by mx.google.com with ESMTPS id m22si10047151pgh.190.2019.08.26.15.33.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Aug 2019 15:33:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 523A66E31D; Mon, 26 Aug 2019 22:33:39 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-oi1-f196.google.com (mail-oi1-f196.google.com [209.85.167.196]) by gabe.freedesktop.org (Postfix) with ESMTPS id 42FD46E319 for ; Mon, 26 Aug 2019 22:33:26 +0000 (UTC) Received: by mail-oi1-f196.google.com with SMTP id t24so13387936oij.13 for ; Mon, 26 Aug 2019 15:33:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jPADKAc1YpBP/58ELuIEmfq6MEoLY9KP0v1RLwFzTo8=; b=MyixUtirrt03G8uxLBT8N1TiME6Sr8NklnSFFRljX65o5XyIdurs18llY/rGeMDFUh Zgd454UfkBa1Rfi5rcmp3+xuWBlU6VMD0k1Fzsd0dYrOF+q3QilwoRQ4DSCKT5dmHYi9 bh9oR491Vx4rsoXVxOC5MwuEmEB5t3d7Bd2uIOMCJ851UyhnRLxRsaJqp1iLPMABePV+ Wuu2yaaopLD6L22xXbS8Gf+XR/mWa15DFb/W/xf7Ys7BW+iiwESchbfHC57jlX8Z9dex JOHEynohPqWGYNwkYYPyAbqgp1FOayV7YBTReiK3akmys1eI6obuwTpnW/6DjZaFCJGh 4t1A== X-Gm-Message-State: APjAAAXSXIzTdvHKnqGqb7mjViTns9E22Ytujj7yQbd3KtiI23e8PKkJ Ai9hSrkjdH7ZbB3BQDnfojVOoUk= X-Received: by 2002:a54:4508:: with SMTP id l8mr8259245oil.90.1566858805090; Mon, 26 Aug 2019 15:33:25 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id e22sm3668959oii.7.2019.08.26.15.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 15:33:24 -0700 (PDT) From: Rob Herring To: dri-devel@lists.freedesktop.org Subject: [PATCH v3 6/8] drm/panfrost: Add cache/TLB flush before switching address space Date: Mon, 26 Aug 2019 17:33:15 -0500 Message-Id: <20190826223317.28509-7-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190826223317.28509-1-robh@kernel.org> References: <20190826223317.28509-1-robh@kernel.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomeu Vizoso , David Airlie , Steven Price , Alyssa Rosenzweig , Robin Murphy Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It's not entirely clear if this is required, but add a flush of GPU caches and TLBs before we change an address space to new page tables. Fixes: 7282f7645d06 ("drm/panfrost: Implement per FD address spaces") Cc: Tomeu Vizoso Cc: Steven Price Cc: Alyssa Rosenzweig Cc: David Airlie Cc: Daniel Vetter Signed-off-by: Rob Herring Reviewed-by: Robin Murphy Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 2 ++ 1 file changed, 2 insertions(+) v3: - New patch -- 2.20.1 diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index 3407b00d0a3a..d1ebde3327fe 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -115,6 +115,8 @@ static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_m u64 transtab = cfg->arm_mali_lpae_cfg.transtab; u64 memattr = cfg->arm_mali_lpae_cfg.memattr; + mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0UL, AS_COMMAND_FLUSH_MEM); + mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL); mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32);