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[131.252.210.177]) by mx.google.com with ESMTPS id l75si2781309pje.36.2019.05.28.01.29.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 May 2019 01:29:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7B7189D57; Tue, 28 May 2019 08:28:58 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by gabe.freedesktop.org (Postfix) with ESMTPS id C4A3C89CCE for ; Tue, 28 May 2019 08:28:40 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x4S8Sa2n036756; Tue, 28 May 2019 03:28:36 -0500 Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x4S8Sai2008861 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 28 May 2019 03:28:36 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 28 May 2019 03:28:34 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 28 May 2019 03:28:34 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x4S8Rxuh125039; Tue, 28 May 2019 03:28:32 -0500 From: Tomi Valkeinen To: , Andrzej Hajda , Laurent Pinchart , Lucas Stach , Andrey Gusakov , Philipp Zabel , Andrey Smirnov , Peter Ujfalusi , Jyri Sarha , Benoit Parrot Subject: [PATCHv4 13/24] drm/bridge: tc358767: remove unnecessary msleep Date: Tue, 28 May 2019 11:27:36 +0300 Message-ID: <20190528082747.3631-14-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190528082747.3631-1-tomi.valkeinen@ti.com> References: <20190528082747.3631-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559032116; bh=rjeMkPPUuniWdBO118d7iYIbarrUJBppNtPQU91XNpg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yECYQIJALN9zXs3zaV2SuGLwap1JLUrHRPBHw0BmCAfTcrpkHkpeGSvvtxAZahowX Y8Uebli0eNYcNAhc282u2s+mL4L0uXdk5uf7vivn9EZSdMqLwh8ZWUB5jE7QOXIvCv GxeiJF07huKBc9yGZVJN9IPLrMgjA/PNJW68O8NQ= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For some reason the driver has a msleep(100) after writing to DP_PHY_CTRL. Toshiba's documentation doesn't suggest any delay is needed, and I have not seen any issues with the sleep removed. Drop it, as msleep(100) is a rather big one. Signed-off-by: Tomi Valkeinen Reviewed-by: Andrzej Hajda Reviewed-by: Andrey Gusakov --- drivers/gpu/drm/bridge/tc358767.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index ccf4c8cfbb52..a60a2e65e468 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -874,7 +874,6 @@ static int tc_main_link_enable(struct tc_data *tc) if (tc->link.base.num_lanes == 2) dp_phy_ctrl |= PHY_2LANE; tc_write(DP_PHY_CTRL, dp_phy_ctrl); - msleep(100); /* PLL setup */ tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);