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[2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id f3si15319108plb.396.2019.04.11.14.53.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Apr 2019 14:53:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A58D089930; Thu, 11 Apr 2019 21:53:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-oi1-f194.google.com (mail-oi1-f194.google.com [209.85.167.194]) by gabe.freedesktop.org (Postfix) with ESMTPS id 866CB89930 for ; Thu, 11 Apr 2019 21:53:16 +0000 (UTC) Received: by mail-oi1-f194.google.com with SMTP id v10so6296324oib.1 for ; Thu, 11 Apr 2019 14:53:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=s4wnVWV3PCmgVISOI1B8KtgOFKECJW5cCP7mTvThq/U=; b=JHW1m1lu73XI2CfAqMZN2yDTxeoIST7Z80EhP/dLPuyXeLstLVifH+OQgVgYQkAEIx C/aMVB+BIqXJMfcPsB8R/RDmAQ3aZZkLlBNGHRONHOfFGtUpAorqcMDORJwZGMkTciN7 P7QE+wdEwfA68sNyfy7Ed94mYPiM1NdttaRF6kTZwjZI/GvGJbS4th0DFJmGc5yPhvvt O/oc2J6aED2Qv4O1RttWBzGk1hEgN8pbWwZHhrM1HXnwy4oGW893vF6XRLglQhektigH fkDc78nSQgni/wfJJDhrSU+eKkHs/DHF2B1/ZmurDvMs7W/NdBNmUZ0yoRo9DH9AbY5V TR/w== X-Gm-Message-State: APjAAAWfU9R69r4dINKTGBT57hIY96IEf5n/DCFP2CBCN46VFzky+8g/ CxrEXAGIxVBz8pQkYeYdyNvYO3w= X-Received: by 2002:aca:4c88:: with SMTP id z130mr7964344oia.170.1555019595450; Thu, 11 Apr 2019 14:53:15 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id j18sm15280624otq.68.2019.04.11.14.53.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 14:53:14 -0700 (PDT) From: Rob Herring To: dri-devel@lists.freedesktop.org Subject: [PATCH] drm/panfrost: Add support for 2MB page entries Date: Thu, 11 Apr 2019 16:53:13 -0500 Message-Id: <20190411215313.1937-1-robh@kernel.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Tomeu Vizoso , Alyssa Rosenzweig Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for 2MB sized pages. This will improve our map and unmap times and save a bit of memory by avoiding 3rd level page tables for contiguous allocations. As we use shmem for buffers and huge page allocations for shmem are off by default, there isn't an improvement out of the box and userspace must enable THP for shmem. It's not clear if the h/w can support 1GB page sizes which standard ARM long format descriptors support. In any case, it is unlikely we'll see any contiguous 1GB allocations on current h/w. Cc: Tomeu Vizoso Cc: David Airlie Cc: Daniel Vetter Signed-off-by: Rob Herring Acked-by: Alyssa Rosenzweig Reviewed-by: Steven Price Acked-by: Tomeu Vizoso --- drivers/gpu/drm/panfrost/panfrost_mmu.c | 32 ++++++++++++++++++------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index 502af37d4b62..762b1bd2a8c2 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -137,6 +137,14 @@ static void mmu_disable(struct panfrost_device *pfdev, u32 as_nr) write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE); } +static size_t get_pgsize(u64 addr, size_t size) +{ + if (addr & (SZ_2M - 1) || size < SZ_2M) + return SZ_4K; + + return SZ_2M; +} + int panfrost_mmu_map(struct panfrost_gem_object *bo) { struct drm_gem_object *obj = &bo->base.base; @@ -165,10 +173,12 @@ int panfrost_mmu_map(struct panfrost_gem_object *bo) dev_dbg(pfdev->dev, "map: iova=%llx, paddr=%lx, len=%zx", iova, paddr, len); while (len) { - ops->map(ops, iova, paddr, SZ_4K, IOMMU_WRITE | IOMMU_READ); - iova += SZ_4K; - paddr += SZ_4K; - len -= SZ_4K; + size_t pgsize = get_pgsize(iova | paddr, len); + + ops->map(ops, iova, paddr, pgsize, IOMMU_WRITE | IOMMU_READ); + iova += pgsize; + paddr += pgsize; + len -= pgsize; } } @@ -202,9 +212,15 @@ void panfrost_mmu_unmap(struct panfrost_gem_object *bo) mutex_lock(&pfdev->mmu->lock); while (unmapped_len < len) { - ops->unmap(ops, iova, SZ_4K); - iova += SZ_4K; - unmapped_len += SZ_4K; + size_t unmapped_page; + size_t pgsize = get_pgsize(iova, len - unmapped_len); + + unmapped_page = ops->unmap(ops, iova, pgsize); + if (!unmapped_page) + break; + + iova += unmapped_page; + unmapped_len += unmapped_page; } mmu_hw_do_operation(pfdev, 0, bo->node.start << PAGE_SHIFT, @@ -342,7 +358,7 @@ int panfrost_mmu_init(struct panfrost_device *pfdev) mmu_write(pfdev, MMU_INT_MASK, ~0); pfdev->mmu->pgtbl_cfg = (struct io_pgtable_cfg) { - .pgsize_bitmap = SZ_4K, // | SZ_2M | SZ_1G), + .pgsize_bitmap = SZ_4K | SZ_2M, .ias = FIELD_GET(0xff, pfdev->features.mmu_features), .oas = FIELD_GET(0xff00, pfdev->features.mmu_features), .tlb = &mmu_tlb_ops,