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[131.252.210.177]) by mx.google.com with ESMTPS id m2si4645026pgp.463.2019.03.26.03.33.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Mar 2019 03:33:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F3B66E7EF; Tue, 26 Mar 2019 10:33:12 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by gabe.freedesktop.org (Postfix) with ESMTPS id C2F956E7E8 for ; Tue, 26 Mar 2019 10:33:00 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2QAWwfV086493; Tue, 26 Mar 2019 05:32:58 -0500 Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2QAWwhr044587 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 26 Mar 2019 05:32:58 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 26 Mar 2019 05:32:57 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 26 Mar 2019 05:32:57 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x2QAWN2E071249; Tue, 26 Mar 2019 05:32:55 -0500 From: Tomi Valkeinen To: Andrzej Hajda , Laurent Pinchart , , Lucas Stach , Andrey Gusakov , Philipp Zabel , Andrey Smirnov , Jyri Sarha , Peter Ujfalusi , Benoit Parrot Subject: [PATCHv2 12/22] drm/bridge: tc358767: remove unnecessary msleep Date: Tue, 26 Mar 2019 12:31:36 +0200 Message-ID: <20190326103146.24795-13-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190326103146.24795-1-tomi.valkeinen@ti.com> References: <20190326103146.24795-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553596378; bh=Y/GI5YL+6+n4P6J+MriGtVKz9CfPUrpmszJbyAEyIDk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UuRkVQDo0ZoB9NCO5C6HrUY//xp72sRWwwIKP1zZrfrRBllOupw7lLCCg4LBC3Ouc d40EEhpIDa7POdYVfuSg0phl/2rigeSr3rTBE84Ty+2aP2WAGhleJmqzzsHIzaXvoB OIYtohJbYY3ZUoAhQsZnHsDFbvAm9WDv0HOjmiIw= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For some reason the driver has a msleep(100) after writing to DP_PHY_CTRL. Toshiba's documentation doesn't suggest any delay is needed, and I have not seen any issues with the sleep removed. Drop it, as msleep(100) is a rather big one. Signed-off-by: Tomi Valkeinen Reviewed-by: Andrzej Hajda Reviewed-by: Andrey Gusakov --- drivers/gpu/drm/bridge/tc358767.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index f628575c9de9..2a6c0c0d47a6 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -872,7 +872,6 @@ static int tc_main_link_enable(struct tc_data *tc) if (tc->link.base.num_lanes == 2) dp_phy_ctrl |= PHY_2LANE; tc_write(DP_PHY_CTRL, dp_phy_ctrl); - msleep(100); /* PLL setup */ tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);