From patchwork Thu Jan 3 11:59:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 154717 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp583881ljp; Thu, 3 Jan 2019 04:07:29 -0800 (PST) X-Google-Smtp-Source: ALg8bN5dfjVnwno5TJU//VAG2i9HBmOhSmshva8C4AGtjCwPVhK3QXmUdYy6Biz0+YasMAyBSSma X-Received: by 2002:a63:9501:: with SMTP id p1mr16921559pgd.149.1546517249525; Thu, 03 Jan 2019 04:07:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546517249; cv=none; d=google.com; s=arc-20160816; b=ItLwDDqLkvXtk3+h/psnq9N54bvGOx9SJvtQja5REZfz6icuWhjLWmENLI3I5rBuJD Vqdl8E7okZq5WCrrTC9Y+ILoQrOAJRSGa8HsR7L2+PgNz13tDJyKV7EDawmk4RDT5yYa xjuHtYWCRdCslvQ/inRniTsDD7d5IOxae6HRGFbx0cj8RxnynK1+I98Hf1wHNkXtEhmU DcLUNm3WU/rlyoL3vw2HSH0fm9XuicBQw3g3EscOb2dpTiOQM0hkRGDVmKNYQZR8lruH a3dD0RA/dNu8+9kXsFcQU9RA7LH0oR9ihEqrzPiciYaqTJyLeqYKNEq3iF8UUwwj/uWD QowQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:delivered-to; bh=0EU0JIhmLRefRecNFkN2xgdiMQjfGp4PWKwl3C5FS7A=; b=loWol2s8MNw+jt5rNP5JQstWv1WU994omLxjFNGSnJJ6DiW/aD4nQio8B6rkPqLx5s 9TIwYpG3YfYbBNy31AIi7QE3xHHYbXYaHr+ugIGQ57yLhq1LXYd0/Y4sdE2s338N7zzh TdsqeIJBBmPjHKFDpJiUk85/IADXgfydbdrqC+QC9U1wOVYk6R4oXoKa3T95kvjoQuu9 h7gyoRkzQeSlp/9gzmmGEoc8F6pzivsYN80QT0DFM/cUrkiJ9K5ZcAWWVpIN4+LBsRyU YQMNiO3nWrEGLpsNyFPD52wESq1UAfDUFes+ruZ76GOdQ/NsGrA0sNrgsiX1LFxkKudt NBEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id d39si11449387pla.278.2019.01.03.04.07.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Jan 2019 04:07:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 681746EAD0; Thu, 3 Jan 2019 12:07:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A2206EACF for ; Thu, 3 Jan 2019 12:07:24 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x03C06ZO056052; Thu, 3 Jan 2019 06:00:06 -0600 Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x03C050n029144 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Jan 2019 06:00:05 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 3 Jan 2019 06:00:05 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 3 Jan 2019 06:00:05 -0600 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x03Bxxgh001514; Thu, 3 Jan 2019 06:00:03 -0600 From: Tomi Valkeinen To: Archit Taneja , Andrzej Hajda , , Andrey Gusakov Subject: [PATCHv2 2/7] drm/bridge: tc358767: add defines for DP1_SRCCTRL & PHY_2LANE Date: Thu, 3 Jan 2019 13:59:49 +0200 Message-ID: <20190103115954.12785-3-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190103115954.12785-1-tomi.valkeinen@ti.com> References: <20190103115954.12785-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen , Laurent Pinchart Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DP1_SRCCTRL register and PHY_2LANE field did not have matching defines. Add these. Signed-off-by: Tomi Valkeinen Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/bridge/tc358767.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 29a7e33e8ae0..5f0a666db2fd 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -142,6 +142,8 @@ #define DP0_LTLOOPCTRL 0x06d8 #define DP0_SNKLTCTRL 0x06e4 +#define DP1_SRCCTRL 0x07a0 + /* PHY */ #define DP_PHY_CTRL 0x0800 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ @@ -150,6 +152,7 @@ #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ +#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ @@ -564,7 +567,7 @@ static int tc_aux_link_setup(struct tc_data *tc) value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; tc_write(SYS_PLLPARAM, value); - tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN); + tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN); /* * Initially PLLs are in bypass. Force PLL parameter update, @@ -834,7 +837,7 @@ static int tc_main_link_setup(struct tc_data *tc) DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 | DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT); /* from excel file - DP1_SrcCtrl */ - tc_write(0x07a0, 0x00003083); + tc_write(DP1_SRCCTRL, 0x00003083); rate = clk_get_rate(tc->refclk); switch (rate) { @@ -855,8 +858,9 @@ static int tc_main_link_setup(struct tc_data *tc) } value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; tc_write(SYS_PLLPARAM, value); + /* Setup Main Link */ - dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN; + dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_2LANE | PHY_A0_EN | PHY_M0_EN; tc_write(DP_PHY_CTRL, dp_phy_ctrl); msleep(100);