From patchwork Wed Sep 26 09:11:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 147553 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp464924lji; Wed, 26 Sep 2018 02:11:05 -0700 (PDT) X-Google-Smtp-Source: ACcGV62bwuBpAoNQkM/S/p60u0X02nUodSOfiqdkAL5j3tPvJM2U+OJ1nnyfR3nQhaZMW6mivmnW X-Received: by 2002:a17:902:b287:: with SMTP id u7-v6mr5011877plr.123.1537953065275; Wed, 26 Sep 2018 02:11:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537953065; cv=none; d=google.com; s=arc-20160816; b=DQuRAjUmgzA7KkfNddpNRd3gGVEFI4H2Ut/JfJVzhnNCqw/s0TvrLif5ygfj6O5+Wd ZA+5YsjFYVayDJzODYFPOxyaIY2IJngXNp2G/tkIvdaBmwYam2c+HOW2JPyFGMJ+QBBD t3IBOJF5GYulzuCkz/M/9XjbsPm725SRTl8+cAjzU2/OeeecKiEzTaG6VRr4xawxyd5E ZL9sTE4lPz+mteG5eij8SZ1adbsD8NM4XhpxwHXebK6WXlGE8DpUlJVlTU2j5n3PMxat y0S7zl3ekmH5VPltqyRzQ5TFjFgvYFAwe8+q6EiBvdkuN/CcJkfGyvRlpqwlLjq6uACt OuGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:delivered-to; bh=/FQl5KYAhFfMSApwlHdgeLZiQQy15YT29yz2vv9CcjI=; b=BupQPFMEDOFhnJR3BUHx4aJ8uXbKrCExDXEVMZ4ycOwZazfOUZYoi+3wPLZuW4TnrZ GCROjAxyL+XISDQNu4THM+ZGkM9J2zqIRzpIjCrpfTt2JGmxjXP1SqSJfSf2merWSI1S 4MF4tXcGsA36WmgEt2tKPxvW4CtOUCYkRAQujh4jbMpVpb9YFQomF1K2NFXqs9Lvkg/f LQdi4zON2W5aYVsarNU6UAwMlz5A8AfVuVKwWULOseu41lD6OVOK1G3qLtffsNiwgD78 tjuRGVcfBNiTdy2exTWyGpZxV9CFAVEK+j8DNIa3f0DwXKkhGCYzYfuRlhCEmXSKcCRG 9xkQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id u68-v6si542698pgb.288.2018.09.26.02.11.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 26 Sep 2018 02:11:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B94106E401; Wed, 26 Sep 2018 09:11:02 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3922C6E3FE for ; Wed, 26 Sep 2018 09:10:56 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w8Q9ArB7093253; Wed, 26 Sep 2018 04:10:53 -0500 Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8Q9Ar1w028295; Wed, 26 Sep 2018 04:10:53 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 26 Sep 2018 04:10:48 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 26 Sep 2018 04:10:48 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w8Q9AinX021168; Wed, 26 Sep 2018 04:10:46 -0500 From: Peter Ujfalusi To: , Subject: [PATCH v4 1/4] drm/omap: fix memory barrier bug in DMM driver Date: Wed, 26 Sep 2018 12:11:27 +0300 Message-ID: <20180926091130.5379-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180926091130.5379-1-peter.ujfalusi@ti.com> References: <20180926091130.5379-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jsarha@ti.com, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tomi Valkeinen A DMM timeout "timed out waiting for done" has been observed on DRA7 devices. The timeout happens rarely, and only when the system is under heavy load. Debugging showed that the timeout can be made to happen much more frequently by optimizing the DMM driver, so that there's almost no code between writing the last DMM descriptors to RAM, and writing to DMM register which starts the DMM transaction. The current theory is that a wmb() does not properly ensure that the data written to RAM is observable by all the components in the system. This DMM timeout has caused interesting (and rare) bugs as the error handling was not functioning properly (the error handling has been fixed in previous commits): * If a DMM timeout happened when a GEM buffer was being pinned for display on the screen, a timeout error would be shown, but the driver would continue programming DSS HW with broken buffer, leading to SYNCLOST floods and possible crashes. * If a DMM timeout happened when other user (say, video decoder) was pinning a GEM buffer, a timeout would be shown but if the user handled the error properly, no other issues followed. * If a DMM timeout happened when a GEM buffer was being released, the driver does not even notice the error, leading to crashes or hang later. This patch adds wmb() and readl() calls after the last bit is written to RAM, which should ensure that the execution proceeds only after the data is actually in RAM, and thus observable by DMM. The read-back should not be needed. Further study is required to understand if DMM is somehow special case and read-back is ok, or if DRA7's memory barriers do not work correctly. Signed-off-by: Tomi Valkeinen Signed-off-by: Peter Ujfalusi --- drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c index f9fa1c90b35c..e84871e74615 100644 --- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c +++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c @@ -285,6 +285,17 @@ static int dmm_txn_commit(struct dmm_txn *txn, bool wait) } txn->last_pat->next_pa = 0; + /* ensure that the written descriptors are visible to DMM */ + wmb(); + + /* + * NOTE: the wmb() above should be enough, but there seems to be a bug + * in OMAP's memory barrier implementation, which in some rare cases may + * cause the writes not to be observable after wmb(). + */ + + /* read back to ensure the data is in RAM */ + readl(&txn->last_pat->next_pa); /* write to PAT_DESCR to clear out any pending transaction */ dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);