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[131.252.210.177]) by mx.google.com with ESMTPS id h1-v6si12503208plt.728.2018.03.07.00.43.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 Mar 2018 00:43:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NVL+jPtI; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CCEAC6E6D6; Wed, 7 Mar 2018 08:43:24 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF1396E6D6 for ; Wed, 7 Mar 2018 08:43:23 +0000 (UTC) Received: by mail-lf0-x244.google.com with SMTP id r80-v6so1995818lfe.13 for ; Wed, 07 Mar 2018 00:43:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=MH0ZOKNUAym5wPRb+PfHLmUdY7SBz0VYdsO/a7ZLxic=; b=NVL+jPtIS+2DAw0sHxd6ATgaSCCAocb9Ns3IHmNJEj+Oe2SF/oRyzm3sDeMvjteNO8 i99AOkHuLRkE1RSl/HlBju4JAXWA7gWFb+45NBjJ6g80BTz6gIcDPFmZVEagfGxmzq6/ f+C5TQClUbckjhQ0Xj3yhRlQlU4k7fw4/ZlCE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=MH0ZOKNUAym5wPRb+PfHLmUdY7SBz0VYdsO/a7ZLxic=; b=WMjBY8MvH+S68LvgOK5ICQmwJOOkARnGwsNpOSPtbSImEaxKd8FD8nDEIpCKX3W8LA gL9oBQW5O6qMN9A4coWckaNGWYCbQzWLT3h/Ht7u1jfhbnr2thWqzYCTqdhCikNaoMns B8ZpJF4aimGNNgHx4H7eB28/e1lJmBgQa15nIW7wEbItfXoyuyb7cVFqpkvKAAO7s83b 4/TqkfHhIJfyuChkQh1Wdqr+IvZIS7LEFOT/uB5D1SqDsUuwiE1JQSYQmJJ/sr/QQaAL 1QMHMeVSHjbjaylXEtCxxf60vZAfLTpiiGpHNbg+OMKgY9KLs/qx0ePGUIao/KHndq1X kCAA== X-Gm-Message-State: APf1xPCGrcVBijhzkeFL4r76pChq7HhSeeYZnwNeAk3ZIsYkZmQvHsqI Liy/E2uqSfyLo5e/yOwaCWxCLQ== X-Received: by 10.46.99.11 with SMTP id x11mr15682334ljb.136.1520412201938; Wed, 07 Mar 2018 00:43:21 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id g26sm3513484ljd.51.2018.03.07.00.43.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 Mar 2018 00:43:20 -0800 (PST) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt , Liviu Dudau Subject: [PATCH 2/4 v4] drm/pl111: Use max memory bandwidth for resolution Date: Wed, 7 Mar 2018 09:43:16 +0100 Message-Id: <20180307084316.23623-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We were previously selecting 1024x768 and 32BPP as the default set-up for the PL111 consumers. This does not work on elder systems: the device tree bindings support a property "max-memory-bandwidth" in bytes/second that states that if you exceed this the memory bus will saturate. The result is flickering and unstable images. Parse the "max-memory-bandwidth" and respect it when intializing the driver. On the RealView PB11MP, Versatile and Integrator/CP we get a nice console as default with this code. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Switch the noisy DRM_INFO for DRM_DEBUG_KMS - Collect Eric's review tag ChangeLog v2->v3: - Account for the case where there is no bandwidth limitation so priv->memory_bw is zero. Then just accept any modes. ChangeLog v1->v2: - Exploit the new .mode_valid() callback we added to the simple KMS helper. - Use the hardcoded bits per pixel per variant instead of trying to be heuristic about this setting for now. --- drivers/gpu/drm/pl111/pl111_display.c | 36 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/pl111/pl111_drm.h | 1 + drivers/gpu/drm/pl111/pl111_drv.c | 6 ++++++ 3 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index d75923896609..72e85397611a 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -50,6 +50,41 @@ irqreturn_t pl111_irq(int irq, void *data) return status; } +static enum drm_mode_status +pl111_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct drm_device *drm = crtc->dev; + struct pl111_drm_dev_private *priv = drm->dev_private; + u32 cpp = priv->variant->fb_bpp / 8; + u64 bw; + + /* + * We use the pixelclock to also account for interlaced modes, the + * resulting bandwidth is in bytes per second. + */ + bw = mode->clock * 1000; /* In Hz */ + bw = bw * mode->hdisplay * mode->vdisplay * cpp; + bw = div_u64(bw, mode->htotal * mode->vtotal); + + /* + * If no bandwidth constraints, anything goes, else + * check if we are too fast. + */ + if (priv->memory_bw && (bw > priv->memory_bw)) { + DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n", + mode->hdisplay, mode->vdisplay, + mode->clock * 1000, cpp, bw); + + return MODE_BAD; + } + DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n", + mode->hdisplay, mode->vdisplay, + mode->clock * 1000, cpp, bw); + + return MODE_OK; +} + static int pl111_display_check(struct drm_simple_display_pipe *pipe, struct drm_plane_state *pstate, struct drm_crtc_state *cstate) @@ -344,6 +379,7 @@ static int pl111_display_prepare_fb(struct drm_simple_display_pipe *pipe, } static const struct drm_simple_display_pipe_funcs pl111_display_funcs = { + .mode_valid = pl111_mode_valid, .check = pl111_display_check, .enable = pl111_display_enable, .disable = pl111_display_disable, diff --git a/drivers/gpu/drm/pl111/pl111_drm.h b/drivers/gpu/drm/pl111/pl111_drm.h index 360fbdd2203c..70b092670c04 100644 --- a/drivers/gpu/drm/pl111/pl111_drm.h +++ b/drivers/gpu/drm/pl111/pl111_drm.h @@ -65,6 +65,7 @@ struct pl111_drm_dev_private { struct drm_simple_display_pipe pipe; void *regs; + u32 memory_bw; u32 ienb; u32 ctrl; /* The pixel clock (a reference to our clock divider off of CLCDCLK). */ diff --git a/drivers/gpu/drm/pl111/pl111_drv.c b/drivers/gpu/drm/pl111/pl111_drv.c index 73d252351438..b469aa317d9d 100644 --- a/drivers/gpu/drm/pl111/pl111_drv.c +++ b/drivers/gpu/drm/pl111/pl111_drv.c @@ -262,6 +262,12 @@ static int pl111_amba_probe(struct amba_device *amba_dev, drm->dev_private = priv; priv->variant = variant; + if (of_property_read_u32(dev->of_node, "max-memory-bandwidth", + &priv->memory_bw)) { + dev_info(dev, "no max memory bandwidth specified, assume unlimited\n"); + priv->memory_bw = 0; + } + /* The two variants swap this register */ if (variant->is_pl110) { priv->ienb = CLCD_PL110_IENB;