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[131.252.210.177]) by mx.google.com with ESMTPS id m23si1539672pfg.11.2017.09.08.05.47.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Sep 2017 05:47:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=CkUDGPyA; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 879996EB29; Fri, 8 Sep 2017 12:47:28 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x234.google.com (mail-lf0-x234.google.com [IPv6:2a00:1450:4010:c07::234]) by gabe.freedesktop.org (Postfix) with ESMTPS id 367036EB35 for ; Fri, 8 Sep 2017 12:47:27 +0000 (UTC) Received: by mail-lf0-x234.google.com with SMTP id d17so5433054lfe.2 for ; Fri, 08 Sep 2017 05:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C/chJQwuGntfluB5Kf5cUea+c/Glat/WRbkaWbl9yuQ=; b=CkUDGPyAhaTocDfNIAsISeozw2TB3noRd7TULsyMfi30TjSMDjYXVFUqw97OVUwYCs ErizfIcGm6TzWgAeimwcegfoLT83giMpnS5KBofYSyc6S2N1yCQ1NKsg8KJIasdEHIyh P90MxwXfdNkT4pVt1fDtcqa60uBNBUvUddYCE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C/chJQwuGntfluB5Kf5cUea+c/Glat/WRbkaWbl9yuQ=; b=C9Y9OYTD6bCJPEAMkPtzK6bCJRjcJvDXoKISlgMFn8QbMsAIKnyA6M1Bt/I3Gs3ett LrfucKaPEHAMVzvTHj44HQXZQzRxsV+/AL1aDDff4l0qqriZ+rgtI4Gmw1yxZKJccL8A 9wM2bYCtgG9vGy/DpVQNbjJEpbjh7tiJ8QA3IEdVMsUYUk/irTBM5cGQzq3vNmVudrlF Ngs7MPeDRcRuZSIslkz3BRrpjPBi9pbUqG4SlhvO33AIU6ePk/Vfoq202EeLeT4Nqyul FgjHWOIHESlHRi0bW0LslcKmSA6ATkqWecRUIJuKDMzdPsY4suvBToqTs+vMBUsCnDI0 eZhw== X-Gm-Message-State: AHPjjUiiwpJrwHwuz90mxRXGX0J9aG3/87f1cDRzn47f/DqLp2e1Gz2z PQ4jl7V6I7NlDwcx X-Google-Smtp-Source: AOwi7QDEBd9jUdGSWL4XSsCgBZH4q9c4pbuom/vbJz4bdJcazTTQvoGzB7TVBFzgk0HFla0O2+JpiQ== X-Received: by 10.46.77.141 with SMTP id c13mr1009239ljd.150.1504874845486; Fri, 08 Sep 2017 05:47:25 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id o28sm317427lfc.9.2017.09.08.05.47.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Sep 2017 05:47:24 -0700 (PDT) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt Subject: [PATCH 5/7 v4] drm/pl111: Insert delay before powering up PL11x Date: Fri, 8 Sep 2017 14:47:07 +0200 Message-Id: <20170908124709.4758-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908124709.4758-1-linus.walleij@linaro.org> References: <20170908124709.4758-1-linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The old codebase has a delay between enabling and powering up the PL11x. According to the manual for PL110, ARM DDI 0161E page 1-5 and the PL111 manual ARM DDI 0293C page 1-6, the power sequence should be such that once Vdd is stable (which we assume it is at boot) LCDEN is enabled first and then CLPOWER should be enabled "after the signals have stabilized" and this is said to be display-dependent. The old codebase uses 20ms. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - No changes. ChangeLog v2->v3: - Rebase on DRM-TIP ChangeLog v1->v2: - Fall back to the delay of 20 ms from the old framebuffer driver to stabilize Vee in shortage of other alternatives. --- drivers/gpu/drm/pl111/pl111_display.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index c08706be4b7e..3091fb4559cf 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -155,8 +155,8 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, writel(0, priv->regs + CLCD_TIM3); - /* Enable and Power Up */ - cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDPWR | CNTL_LCDVCOMP(1); + /* Hard-code TFT panel */ + cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1); /* Note that the the hardware's format reader takes 'r' from * the low bit, while DRM formats list channels from high bit @@ -199,6 +199,17 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, break; } + /* Power sequence: first enable and chill */ + writel(cntl, priv->regs + priv->ctrl); + + /* + * We expect this delay to stabilize the contrast + * voltage Vee as stipulated by the manual + */ + msleep(20); + + /* Power Up */ + cntl |= CNTL_LCDPWR; writel(cntl, priv->regs + priv->ctrl); drm_crtc_vblank_on(crtc); @@ -209,10 +220,24 @@ void pl111_display_disable(struct drm_simple_display_pipe *pipe) struct drm_crtc *crtc = &pipe->crtc; struct drm_device *drm = crtc->dev; struct pl111_drm_dev_private *priv = drm->dev_private; + u32 cntl; drm_crtc_vblank_off(crtc); - /* Disable and Power Down */ + /* Power Down */ + cntl = readl(priv->regs + priv->ctrl); + if (cntl & CNTL_LCDPWR) { + cntl &= ~CNTL_LCDPWR; + writel(cntl, priv->regs + priv->ctrl); + } + + /* + * We expect this delay to stabilize the contrast voltage Vee as + * stipulated by the manual + */ + msleep(20); + + /* Disable */ writel(0, priv->regs + priv->ctrl); clk_disable_unprepare(priv->clk);