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[131.252.210.177]) by mx.google.com with ESMTPS id t202si1568333pgb.82.2017.09.01.02.37.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 02:37:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=BaG9IlpU; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3556B6E810; Fri, 1 Sep 2017 09:37:01 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x22a.google.com (mail-lf0-x22a.google.com [IPv6:2a00:1450:4010:c07::22a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8CF876E810 for ; Fri, 1 Sep 2017 09:36:59 +0000 (UTC) Received: by mail-lf0-x22a.google.com with SMTP id a126so7330939lfa.0 for ; Fri, 01 Sep 2017 02:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=an3gtzWdE/JgZ3IsQ/Zpzj+/Nm/X5XRYs8T2AJSjgtM=; b=BaG9IlpUxpKatwra/cTewT/Sv/MdxR3B5f/gzr2EEcMax7CgmozqR3bcaz1Tq8bqEa vquQo4xCERtR68JSlAwdPHdeLHSvXY9B/kszTLmb1ioxbz8r41Tj5C/8bRxQ9L1THUf0 C6BRfT2NNTjGTKuHKNNVyqtH2Y1o886n42xVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=an3gtzWdE/JgZ3IsQ/Zpzj+/Nm/X5XRYs8T2AJSjgtM=; b=nzTRd/70/1hJTh4pEDXDcOHx6uPZM3Zl4ZVCf+YAu19Uq7u3JXXli9l5pP6B8BJ2O4 R7SISbkZ/us0BfWfiPkskCcmsztyYxNRJA1Ik54MsBI3p8LxCGxIbPXRt4DW/HF0lu2a CbueYZYryCWIfMFcR+SFoPaOT6k9Jew0Ooj5P3QBU3LNGpKuriDQqKep/4Op8OUQOS+4 XSfov7QbiXsj8829BWarzpPxjIDs+nQ9xEsG7Rn0lNydsPS54hKuIPtLCMVP2pkIMahO GkO+kdlhWbJQKHM2y2YvR+iZRny3Lb4RMFEXb9m/Jkh43Snka/GaoHw95FNBWzhFSYEo A44g== X-Gm-Message-State: AHPjjUiD18qOolg5dTroRB31kIg577qQEUodTJzdQnfWayQ8Edl2NMkO 4NDFk947CKdEwB2q X-Google-Smtp-Source: ADKCNb5H6+awbBjg5iRMqnMEPLdLhlPDKjjStuzW7CT3sVThAqoyWsKjJGqqXuucAoLjUL80Qbva5g== X-Received: by 10.25.26.7 with SMTP id a7mr636624lfa.196.1504258617965; Fri, 01 Sep 2017 02:36:57 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id x18sm328588ljd.85.2017.09.01.02.36.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Sep 2017 02:36:57 -0700 (PDT) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt Subject: [PATCH 5/7 v2] drm/pl111: Insert delay before powering up PL11x Date: Fri, 1 Sep 2017 11:36:35 +0200 Message-Id: <20170901093637.4041-6-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170901093637.4041-1-linus.walleij@linaro.org> References: <20170901093637.4041-1-linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The old codebase has a delay between enabling and powering up the PL11x. According to the manual for PL110, ARM DDI 0161E page 1-5 and the PL111 manual ARM DDI 0293C page 1-6, the power sequence should be such that once Vdd is stable (which we assume it is at boot) LCDEN is enabled first and then CLPOWER should be enabled "after the signals have stabilized" and this is said to be display-dependent. The old codebase uses 20ms. Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Fall back to the delay of 20 ms from the old framebuffer driver to stabilize Vee in shortage of other alternatives. --- drivers/gpu/drm/pl111/pl111_display.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index 51e3530c876c..3ed451ca2744 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -154,8 +154,8 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, writel(0, priv->regs + CLCD_TIM3); - /* Enable and Power Up */ - cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDPWR | CNTL_LCDVCOMP(1); + /* Hard-code TFT panel */ + cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1); /* Note that the the hardware's format reader takes 'r' from * the low bit, while DRM formats list channels from high bit @@ -198,6 +198,17 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, break; } + /* Power sequence: first enable and chill */ + writel(cntl, priv->regs + priv->ctrl); + + /* + * We expect this delay to stabilize the contrast + * voltage Vee as stipulated by the manual + */ + msleep(20); + + /* Power Up */ + cntl |= CNTL_LCDPWR; writel(cntl, priv->regs + priv->ctrl); drm_crtc_vblank_on(crtc); @@ -208,10 +219,24 @@ void pl111_display_disable(struct drm_simple_display_pipe *pipe) struct drm_crtc *crtc = &pipe->crtc; struct drm_device *drm = crtc->dev; struct pl111_drm_dev_private *priv = drm->dev_private; + u32 cntl; drm_crtc_vblank_off(crtc); - /* Disable and Power Down */ + /* Power Down */ + cntl = readl(priv->regs + priv->ctrl); + if (cntl & CNTL_LCDPWR) { + cntl &= ~CNTL_LCDPWR; + writel(cntl, priv->regs + priv->ctrl); + } + + /* + * We expect this delay to stabilize the contrast voltage Vee as + * stipulated by the manual + */ + msleep(20); + + /* Disable */ writel(0, priv->regs + priv->ctrl); clk_disable_unprepare(priv->clk);