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[82.242.157.225]) by smtp.gmail.com with ESMTPSA id w7sm8888886wmd.24.2016.12.07.02.43.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Dec 2016 02:43:04 -0800 (PST) From: Bartosz Golaszewski To: Jyri Sarha , Tomi Valkeinen , David Airlie , Kevin Hilman , Michael Turquette , Sekhar Nori , Rob Herring , Frank Rowand , Mark Rutland , Laurent Pinchart , Peter Ujfalusi , Russell King Subject: [PATCH v5 4/4] ARM: dts: da850: specify the maximum pixel clock rate for tilcdc Date: Wed, 7 Dec 2016 11:42:45 +0100 Message-Id: <1481107365-24839-5-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1481107365-24839-1-git-send-email-bgolaszewski@baylibre.com> References: <1481107365-24839-1-git-send-email-bgolaszewski@baylibre.com> Cc: linux-devicetree , linux-drm , LKML , arm-soc , Bartosz Golaszewski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" At maximum CPU frequency of 300 MHz the maximum pixel clock frequency is 37.5 MHz[1]. We must filter out any mode for which the calculated pixel clock rate would exceed this value. Specify the max-pixelclock property for the display node for da850-lcdk. [1] http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_LCD_Controller_(LCDC)_Throughput_and_Optimization_Techniques Signed-off-by: Bartosz Golaszewski --- arch/arm/boot/dts/da850.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 3f51e59..ba5bf80 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -452,6 +452,7 @@ compatible = "ti,da850-tilcdc"; reg = <0x213000 0x1000>; interrupts = <52>; + max-pixelclock = <37500>; status = "disabled"; }; };