From patchwork Thu Sep 29 16:43:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 77141 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp452515qgf; Thu, 29 Sep 2016 09:44:09 -0700 (PDT) X-Received: by 10.98.14.20 with SMTP id w20mr3999077pfi.9.1475167449885; Thu, 29 Sep 2016 09:44:09 -0700 (PDT) Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id q17si15031212pfg.98.2016.09.29.09.44.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Sep 2016 09:44:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FDBC6E8AF; Thu, 29 Sep 2016 16:44:08 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm0-x229.google.com (mail-wm0-x229.google.com [IPv6:2a00:1450:400c:c09::229]) by gabe.freedesktop.org (Postfix) with ESMTPS id 781BE6E8AF for ; Thu, 29 Sep 2016 16:44:06 +0000 (UTC) Received: by mail-wm0-x229.google.com with SMTP id w72so38259951wmf.1 for ; Thu, 29 Sep 2016 09:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=vzJ5EU2lT8vjt/upXiU+D9BrxWWGoR7+WAf5gozaXPs=; b=BAJIwEmOQgCEy0UHzP7nPNaV8WPrWv39Y0ll+90rn5ALfVNaBf/JPKPeA4kE2l+F3D ol7mY13MhUi0CJ/SxB4DE+cqDukea64XmMNiLvUb+ORsOylFsch/UtwIPAMHqXnYuxPS OMOk40kQP5EVNNjZZVfj7h5/bXn6X8aN99W50EZHrYPAy/3EnHMKNPRGpDUzuiVyoh/R RHrzwu8KXvlF4z5/uQbHNhx5h1UD9FyQWVm5Xf4C+83Dr8wi4jrxXjoOm3aDJOc8t8nP flxyeqL7/rQQ0aZojS+BOkUk54IQswwy8Y6vCH9GbQv3KQ8U2e7AjAFWmQOSVXBWg6yF cCdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vzJ5EU2lT8vjt/upXiU+D9BrxWWGoR7+WAf5gozaXPs=; b=mK62cQsGW7jU6QsjynSNiPJRIYw5iQwsclUlgAE7Q6Uste92/is8kLkUbw8cRJqe3v 8IhaXJDN5Wp8u5Tl0XApA0Ib+skGNlmtCbOIhJAd1LWo3IhNX0AaS+kNF95cux6ffr6M r2lEDDGPc9EyvAABj5YoJ057tFXooOQd9wUCq8RPn3ZjPmKFZjENmD1ahJRMQnyggc3/ sZ6bNujVvmFRtLnvif9HCXuQQiQTII31G1/aZe5vZ46WOFOun3i2ucg+kWEXeUOy/Tjb 4ZZ2DkDct7rJzCH5u0CTe5/mfWBTGXxEp5i/xgIQu5F3bbrJnvsx5k8r1X/t9H+f4vyh ct+Q== X-Gm-Message-State: AA6/9RkhDp/hpO6dcTKjzEM/qnTnXFurnu0aD4gdg8oSpxzN+7ydJ+w0IFmY8M6u25iP2p4E X-Received: by 10.28.69.68 with SMTP id s65mr3861504wma.127.1475167445102; Thu, 29 Sep 2016 09:44:05 -0700 (PDT) Received: from bgdev-debian.lan (jua06-1-82-242-157-225.fbx.proxad.net. [82.242.157.225]) by smtp.gmail.com with ESMTPSA id q65sm15458915wmd.24.2016.09.29.09.44.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Sep 2016 09:44:04 -0700 (PDT) From: Bartosz Golaszewski To: Jyri Sarha , Tomi Valkeinen , David Airlie , Kevin Hilman , Michael Turquette , Sekhar Nori Subject: [PATCH v3] drm: tilcdc: add a workaround for failed clk_set_rate() Date: Thu, 29 Sep 2016 18:43:57 +0200 Message-Id: <1475167437-8920-1-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 Cc: Bartosz Golaszewski , LKML , linux-drm X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some architectures don't use the common clock framework and don't implement all the clk interfaces for every clock. This is the case for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1. Trying to set the clock rate for the LCDC clock results in -EINVAL being returned. As a workaround for that: if the call to clk_set_rate() fails, fall back to adjusting the clock divider instead. Proper divider value is calculated by dividing the current clock rate by the required pixel clock rate in HZ. This code is based on a hack initially developed internally for baylibre by Karl Beldan . Tested with a da850-lcdk with an LCD display connected over VGA. Signed-off-by: Bartosz Golaszewski --- v1 -> v2: - rebased on top of current drm-next - removed unnecessary error messages - removed an extra newline - added a warning if the effective pixel clock rate differs much from the requested rate v2 -> v3: - removed WARN_ONCE() in favor of dev_warn() - added the real and calculated clock rates to the warning message - tweaked the variable names - used a local variable to remove redundant 'crtc->mode.clock * 1000' Retested with modetest -M tilcdc -s 26:800x600@RG16 modetest -M tilcdc -s 26:1024x768@RG16 using some additional work-in-progress changes on top of this patch. drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 57 ++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 52ebe8f..87cfde9 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -320,23 +320,68 @@ static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, return true; } +/* + * Calculate the percentage difference between the requested pixel clock rate + * and the effective rate resulting from calculating the clock divider value. + */ +static unsigned int tilcdc_pclk_diff(unsigned long rate, + unsigned long real_rate) +{ + int r = rate / 100, rr = real_rate / 100; + + return (unsigned int)(abs(((rr - r) * 100) / r)); +} + static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct tilcdc_drm_private *priv = dev->dev_private; struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - const unsigned clkdiv = 2; /* using a fixed divider of 2 */ + unsigned long clk_rate, real_rate, req_rate; + unsigned int clkdiv; int ret; + clkdiv = 2; /* first try using a standard divider of 2 */ + /* mode.clock is in KHz, set_rate wants parameter in Hz */ - ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); + req_rate = crtc->mode.clock * 1000; + + ret = clk_set_rate(priv->clk, req_rate * clkdiv); + clk_rate = clk_get_rate(priv->clk); if (ret < 0) { - dev_err(dev->dev, "failed to set display clock rate to: %d\n", - crtc->mode.clock); - return; + /* + * If we fail to set the clock rate (some architectures don't + * use the common clock framework yet and may not implement + * all the clk API calls for every clock), try the next best + * thing: adjusting the clock divider, unless clk_get_rate() + * failed as well. + */ + if (!clk_rate) { + /* Nothing more we can do. Just bail out. */ + dev_err(dev->dev, + "failed to set the pixel clock - unable to read current lcdc clock rate\n"); + return; + } + + clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate); + + /* + * Emit a warning if the real clock rate resulting from the + * calculated divider differs much from the requested rate. + * + * 5% is an arbitrary value - LCDs are usually quite tolerant + * about pixel clock rates. + */ + real_rate = clkdiv * req_rate; + + if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) { + dev_warn(dev->dev, + "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n", + clk_rate, real_rate); + } } - tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk); + tilcdc_crtc->lcd_fck_rate = clk_rate; DBG("lcd_clk=%u, mode clock=%d, div=%u", tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);