From patchwork Fri Jun 28 16:35:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honnappa Nagarahalli X-Patchwork-Id: 168106 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3910439ilk; Fri, 28 Jun 2019 09:35:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3wAuiWUvPRz8g/jq+iNPfLiErGaIoZgAQDA0236VEl1tfM5l8z8ACNwL+mrxNxnk4YTLI X-Received: by 2002:a7b:ce95:: with SMTP id q21mr7914981wmj.65.1561739759290; Fri, 28 Jun 2019 09:35:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561739759; cv=none; d=google.com; s=arc-20160816; b=R4r32mwseIIAVA6S94O9RWys6OMSbDiDiiaybFbBBVONCemR/puUigHWVek2HtLhVV tIdmTdGekTxgGLlPHdS372axZ76+eKBV4SQeKF6Ddreu8NZ2uxVySTjtEvVDL9U9zp+g Kc9rZPUva2WXO94wc5CtxbYv+1vDEzhyRdMltSYHzwsUeHnl9O1HL570NXlYI6sBJunq qYRHBQt3kwrL5VVVRA7nRQ5EbZ4Z1ZmshcjYJZ7nKboaJfas5xNxwfFUCHbE4zs+3LGe 82GpxjPvTP6fv0mCTfRxDJ1xqkX0wTefIYDlqfFpbuIbXWEz4Z2hel4/nGBUgPsARzlM dJyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=qVSsoEH7jqLWSpp3BnuI3jfDiP3ape/idjAFC1/sSe8=; b=LVWY/cqJb/P4pMNFCmqNkOppDHDH99ouDoKI3gQk15M+78lzJYOZYoZ+lvcylRK4jT dIo64bBc7AD8R7CHNWvQ+6ZUGvDY48ul21BeTYBKCJv0zuf1tXo5TP/IKFSLlXKxafzr BKxfxUV0hB5YGBcwOzTpycfusQl+5K3r3Oqz+WhaHiz1DAVV7crW+4RnoSqAtlJlK3Dt OAux+TB1ppyZr9qrquWVUTDaBEfesVyNnyQA3vi/6Cz/eE6w/e5ZnAey8OydNawIC9qa Za1PyrMagJX6UuXGwzHFo5D0oedEXgPkj8EpSy/LQGIJAGGH5Y4uTsKbF4xfJngDihhC +lvA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id h9si2051349wrw.73.2019.06.28.09.35.59; Fri, 28 Jun 2019 09:35:59 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C8A6B49DF; Fri, 28 Jun 2019 18:35:57 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 2D56B37B4; Fri, 28 Jun 2019 18:35:56 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7735B28; Fri, 28 Jun 2019 09:35:55 -0700 (PDT) Received: from qc2400f-1.austin.arm.com (qc2400f-1.austin.arm.com [10.118.12.65]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 594F93F706; Fri, 28 Jun 2019 09:35:55 -0700 (PDT) From: Honnappa Nagarahalli To: honnappa.nagarahalli@arm.com Cc: dev@dpdk.org, david.marchand@redhat.com, thomas@monjalon.net, ferruh.yigit@intel.com, ruifeng.wang@arm.com, nd@arm.com, stable@dpdk.org Date: Fri, 28 Jun 2019 11:35:48 -0500 Message-Id: <20190628163549.29160-1-honnappa.nagarahalli@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628034406.5399-1-honnappa.nagarahalli@arm.com> References: <20190628034406.5399-1-honnappa.nagarahalli@arm.com> Subject: [dpdk-dev] [PATCH v2 1/2] test/rcu: increase the size of num cores variable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" num_cores is of type uint8_t. This results in the following compilation error. test_rcu_qsbr_perf.c:649:16: error: comparison is always false due to limited range of data type [-Werror=type-limits] if (num_cores >= RTE_MAX_LCORE) { ^~ RTE_MAX_LCORE is set to 256 for armv8 config. Fixes: e6a14121f4ae ("test/rcu: remove arbitrary limit on max core count") Cc: stable@dpdk.org Signed-off-by: Honnappa Nagarahalli Reviewed-by: Ruifeng Wang --- v2 - Changed type of num_cores to 'unsigned int' and related changes (David/Thomas) app/test/test_rcu_qsbr.c | 8 ++++---- app/test/test_rcu_qsbr_perf.c | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/app/test/test_rcu_qsbr.c b/app/test/test_rcu_qsbr.c index 943a1e370..ae359a987 100644 --- a/app/test/test_rcu_qsbr.c +++ b/app/test/test_rcu_qsbr.c @@ -27,7 +27,7 @@ #define TEST_RCU_QSBR_CNT_INIT 1 uint16_t enabled_core_ids[RTE_MAX_LCORE]; -uint8_t num_cores; +unsigned int num_cores; static uint32_t *keys; #define TOTAL_ENTRY (1024 * 8) @@ -389,7 +389,7 @@ test_rcu_qsbr_synchronize_reader(void *arg) static int test_rcu_qsbr_synchronize(void) { - int i; + unsigned int i; printf("\nTest rte_rcu_qsbr_synchronize()\n"); @@ -890,8 +890,8 @@ test_rcu_qsbr_sw_sv_3qs(void) static int test_rcu_qsbr_mw_mv_mqs(void) { - int i, j; - uint8_t test_cores; + unsigned int i, j; + unsigned int test_cores; writer_done = 0; test_cores = num_cores / 4; diff --git a/app/test/test_rcu_qsbr_perf.c b/app/test/test_rcu_qsbr_perf.c index 363365f46..a085db852 100644 --- a/app/test/test_rcu_qsbr_perf.c +++ b/app/test/test_rcu_qsbr_perf.c @@ -17,7 +17,7 @@ /* Check condition and return an error if true. */ static uint16_t enabled_core_ids[RTE_MAX_LCORE]; -static uint8_t num_cores; +static unsigned int num_cores; static uint32_t *keys; #define TOTAL_ENTRY (1024 * 8) @@ -125,8 +125,8 @@ test_rcu_qsbr_writer_perf(void *arg) static int test_rcu_qsbr_perf(void) { - int i, sz; - int tmp_num_cores; + unsigned int i, sz; + unsigned int tmp_num_cores; writer_done = 0; @@ -188,8 +188,8 @@ test_rcu_qsbr_perf(void) static int test_rcu_qsbr_rperf(void) { - int i, sz; - int tmp_num_cores; + unsigned int i, sz; + unsigned int tmp_num_cores; rte_atomic64_clear(&updates); rte_atomic64_clear(&update_cycles); @@ -234,7 +234,7 @@ test_rcu_qsbr_rperf(void) static int test_rcu_qsbr_wperf(void) { - int i, sz; + unsigned int i, sz; rte_atomic64_clear(&checks); rte_atomic64_clear(&check_cycles); @@ -378,7 +378,7 @@ static int test_rcu_qsbr_sw_sv_1qs(void) { uint64_t token, begin, cycles; - int i, j, tmp_num_cores, sz; + unsigned int i, j, tmp_num_cores, sz; int32_t pos; writer_done = 0; @@ -496,7 +496,7 @@ static int test_rcu_qsbr_sw_sv_1qs_non_blocking(void) { uint64_t token, begin, cycles; - int i, j, ret, tmp_num_cores, sz; + unsigned int i, j, ret, tmp_num_cores, sz; int32_t pos; writer_done = 0;